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A3P030 Schematic ( PDF Datasheet ) - Actel Corporation

Teilenummer A3P030
Beschreibung (A3Pxxx) ProASIC3 Flash Family FPGAs
Hersteller Actel Corporation
Logo Actel Corporation Logo 




Gesamt 30 Seiten
A3P030 Datasheet, Funktion
www.DataSheet4U.com
ProASIC3 Flash Family FPGAs
Advanced v0.2
Features and Benefits
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 288 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live-At-Power-Up Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM (FROM)
Performance
• 150+ MHz Internal System Performance with 3.3 V,
66 MHz 64-bit PCI (except A3P030)
• Up to 350 MHz External System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit AES Decryption via
JTAG (IEEE1532-compliant) (except A3P030)
• FlashLock™ to Secure FPGA Contents
Low Power
• 1.5 V Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL and LVDS (A3P250
and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable I/Os (A3P030 only)
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/Down
• IEEE1149.1 (JTAG) Boundary-Scan Test
• Pin-Compatible Packages Across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
(except A3P030)
• Six CCC Blocks Total, One with an Integrated PLL
• Flexible Phase Shift, Multiply/Divide, and Delay
Capabilities
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs (except A3P030)
• Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
• True Dual-Port SRAM (except x18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
• Programmable Embedded FIFO Control Logic
Table 1 • ProASIC3 Product Family
System Gates
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM (FROM) Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals1
I/O Banks
Maximum User I/Os
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
A3P030
30 k
768
1k
6
2
81
QN132
VQ100
A3P060
60 k
1,536
18
4
1k
Yes
1
18
2
96
VQ100
TQ144
FG144
A3P125
125 k
3,072
36
8
1k
Yes
1
18
2
133
A3P250
250 k
6,144
36
8
1k
Yes
1
18
4
157
A3P400
400 k
9,216
54
12
1k
Yes
1
18
4
194
A3P600
600 k
13,824
108
24
1k
Yes
1
18
4
227
A3P1000
1M
24,576
144
32
1k
Yes
1
18
4
288
VQ100
TQ144
PQ208
FG144
VQ100
PQ208
PQ208
PQ208
PQ208
FG144, FG256 FG144, FG256, FG144, FG256, FG144,
FG484
FG484
FG256, FG484
Notes:
1. Six chip (main) and three quadrant global networks are available for A3P060 and above.
2. For higher densities and support of additional features, refer to the ProASIC3E Flash FPGAs datasheet.
January 2005
© 2005 Actel Corporation
i
See Actel’s website for the latest version of the datasheet.






A3P030 Datasheet, Funktion
www.DataSheet4U.com
ProASIC3 Flash Family FPGAs
Single Chip
Flash-based FPGAs store the configuration information
in on-chip Flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure and no external configuration data needs to be
loaded at system power-up (unlike SRAM-based FPGAs).
Therefore, Flash-based ProASIC3 FPGAs do not require
system configuration components such as EEPROMs or
microcontrollers to load the device configuration data.
This reduces bill-of-materials costs and printed circuit
board (PCB) area, and increases security and system
reliability.
Live at Power-Up
Actel’s Flash-based ProASIC3 devices support Level 0 of
the live-at-power-up classification standard, hence
helping in system components initialization, executing
critical tasks before the processor wakes up, setup and
configure memory blocks, clock generation, and bus
activity management. The live-at-power-up feature of
Flash-based ProASIC3 devices greatly simplifies total
system design and reduces total system cost, often
eliminating the need for Complex Programmable Logic
Device (CPLD) and clock generation PLL that are used for
this purpose in a system. In addition, glitches and
brownouts in system power will not corrupt the
ProASIC3 device’s Flash configuration, and unlike SRAM-
based FPGAs, the device will not have to be reloaded
when system power is restored. This enables the
reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection,
and clock generator devices from the PCB design. Flash-
based ProASIC3 devices simplify total system design, and
reduce cost and design risk, while increasing system
reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of ProASIC3 Flash-
based FPGAs. Once it is programmed, the Flash cell
configuration element of ProASIC3 FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power
characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3 devices
have only a very limited power-on current surge, and no
high-current transition period, both of which occur on
many FPGAs.
ProASIC3 devices also have low dynamic power
consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3 family offers many benefits, including
nonvolatility and reprogrammability through an
advanced Flash-based, 130-nm LVCMOS process with
seven layers of metal. Standard CMOS design techniques
are used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides
granularity comparable to standard-cell ASICs. The
ProASIC3 device consists of five distinct and
programmable architectural features (Figure 1-1 on page
1-3 and Figure 1-2 on page 1-3):
• Dedicated FlashROM (FROM) memory
• Dedicated SRAM/FIFO memory1
• Extensive clock conditioning circuitry (CCC) and
PLLs1
• Advanced I/O structure
• FPGA VersaTiles
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic
function or a D-flip-flop (with or without enable) or latch
by programming the appropriate Flash switch
interconnections. The versatility of the ProASIC3 core tile
as either a three-input look-up-table (LUT) equivalent or
a D-flip-flop/latch with enable allows for efficient use of
the FPGA fabric. The VersaTile capability is unique to the
Actel ProASIC families of Flash-based FPGAs. VersaTiles
are connected with any of the four levels of routing
hierarchy. Flash switches are distributed throughout the
device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is
possible for virtually any design.
In addition, extensive on-chip programming circuitry
allows for rapid, single-voltage (3.3 V) programming of
the ProASIC3 devices via an IEEE1532 JTAG interface.
1. The A3P030 device does not support PLL and SRAM.
1-2 Advanced v0.2

6 Page









A3P030 pdf, datenblatt
www.DataSheet4U.com
ProASIC3 Flash Family FPGAs
Device Overview
The ProASIC3 device family consists of five distinct
programmable architectural features (Figure 2-2 and
Figure 2-3 on page 2-3):
• FPGA fabric/core (VersaTiles)
• Routing and clock resources (VersaNets)
• FlashROM (FROM) memory
• Dedicated SRAM/FIFO memory (except A3P030)
• Advanced I/O structure
Core Architecture
VersaTile
The proprietary ProASIC3 family architecture provides
granularity comparable to gate arrays. The ProASIC3
device core consists of a sea-of-VersaTiles architecture.
As illustrated in Figure 2-4 on page 2-4, there are four
inputs in a logic VersaTile cell, and each VersaTile can be
configured using the appropriate Flash switch
connections:
• Any three-input logic function
• Latch with clear or set
• D-flip-flop with clear or set
• Enable D-flip-flop with clear or set (on a fourth
input)
VersaTiles can flexibly map the logic and sequential gates
of a design. The inputs of the VersaTile can be inverted
(allowing bubble pushing), and the output of the tile can
connect to high-speed, very-long-line routing resources.
VersaTiles and larger functions are connected with any of
the four levels of routing hierarchy.
When the VersaTile is used as an enable D-flip-flop, the
SET/CLR is supported by a fourth input. The fourth input
is routed to the core cell over the VersaNet (global)
network.
The SET/CLR signal can only be routed to this fourth
input over the VersaNet (global) network. However, if in
the user design, the SET/CLR signal is not routed over the
VersaNet network, a compile warning message will be
given and the intended logic function will be
implemented by two VersaTiles instead of one.
The output of the VersaTile is F2 when the connection is
to the ultra-fast local lines, or YL when connection is to
the efficient long-lines or very-long-lines resources.
Bank 0
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
ISP AES
Decryption*
User Nonvolatile
FlashROM (FROM)
Bank 1
Charge Pumps
Note: *Not supported by A3P030.
Figure 2-2 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)
2-2 Advanced v0.2

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