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PDF EM6521 Data sheet ( Hoja de datos )
| Número de pieza | EM6521 | |
| Descripción | 4 bit Microcontroller | |
| Fabricantes | ETC | |
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EMwww.DataSheet4U.com
MICROELECTRONIC
-
MARIN
SA
EM6521
MFP version of EM6621
Ultra Low Power Microcontroller with 4x20 LCD Driver
Features
• Low Power - 11 µA active mode, LCD On
- 1.8 µA standby mode, LCD Off
- 0.1 µA sleep mode
@ 3 V, 32 KHz, 25 ºC
• Large Voltage range, 2 to 5.5 V
• 2 clocks per instruction cycle
• 72 basic instructions
• EEPROM 4096 x 16 bits
• RAM 128 x 4 bits
• Max. 12 inputs ; port A, port B, port SP
• Max. 8 outputs ; port B, port SP
• Voltage Level Detector, 8 levels software
selectable from 1.2 V up to 4.0 V
• Melody, 7 tones + silence inclusive 4-bit timer
• Universal 10-bit counter, PWM, event counter
• Prescaler down to 1 second ( crystal = 32 KHz )
• 1/1000 sec 12 bit binary coded decimal counter
with hard or software start/stop function
• LCD 20 Segments, 3 or 4 times multiplexed
• 3 wire serial port , 8 bit, master and slave mode
• 5 external interrupts (port A, serial interface)
• 8 internal interrupts (3x prescaler, BCD counter
2x10-bit counter, melody timer, serial interface)
• timer watchdog and oscillation supervisor
Description
The EM6521 is an advanced single chip CMOS 4-bit
microcontroller. It contains EEPROM, RAM, LCD
driver, power on reset, watchdog timer, oscillation
detection circuit, 10-bit up/down and event counter,
1ms BCD counter, prescaler, voltage level detector
(Vld), serial interface and several clock functions. The
low voltage feature and low power consumption make
it the most suitable controller for battery, stand alone
and mobile equipment. The EM6521 is manufactured
using EM Marin's Advanced Low Power (ALP) CMOS
Process.
Figure 1. Architecture
Figure 2. Pin Configuration, TQFP52 10 * 10 * 1 mm
Typical Applications
• Timing device
• Automotive controls with display
• Intelligent display driver
• Measurement equipment
• Domestic appliance
• Interactive system with display
• Timer / sports timing devices
• Bicycle computers
• Safety and security devices
Copyright © 2005, EM Microelectronic-Marin SA
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EM6521
Chip TQFP DIL Signal Name
Function
Remarks
52 64
35 35
51
PB[1]
Input/output, open drain
Port B data[1] I/O or
port B terminal 1
Ck[11] output
36 36
52
PB[2]
Input/output, open drain
Port B data[2] I/O or
port B terminal 2
Ck[16] output
37 37
53
PB[3]
Input/output, open drain
Port B data[3] I/O or
port B terminal 3
PWM output
38 38
54
PA[0]
Input port A terminal 0
TestVar 1
Event counter
39 39
55
PA[1]
Input port A terminal 1
TestVar 2
40 40
58
PA[2]
Input port A terminal 2
TestVar 3
41 41
59
PA[3]
Input port A terminal 3
Event counter,
MSC start/stop control
42 42
60
Buzzer
Output Buzzer terminal
43 43
61
Strobe
Output Strobe terminal
µP reset state or/and port B
write or sleep flag out
44 44
45 45
62
63
VBAT = VDD
Vreg
Positive power supply
Internal voltage regulator
MFP Connection
Connect to minimum 100nF,
MFP connection
46 46
64
Qin/Osc1
Crystal terminal 1
32 KHz crystal, MFP connection
47 47 2 Qout /Osc2
Crystal terminal 2
32 KHz crystal, MFP connection
48 48
49 49
3
4
VSS
C2B
Negative power supply
Voltage multiplier
ref. terminal, MFP connection
Not needed if ext. supply
50 50
5
C2A
Voltage multiplier
Not needed if ext. supply
51 51
6
C1B
Voltage multiplier
Not needed if ext. supply
52 52
7
C1A
Voltage multiplier
Not needed if ext. supply
Gray shaded areas : Terminals needed for MFP programming connections (VDD, Vreg, Qin, Qout, Test). See
also Programming connections.
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than
circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA
reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged
to ensure that the information given has not been superseded by a more up-to-date version.
Copyright © 2005, EM Microelectronic-Marin SA
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EM6521
4.4 Digital Watchdog Timer Reset
The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will
generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by
activating an inhibit digital watchdog bit (NoLogicWD) located in RegVldCntl. At power up, and after any
system reset, the watchdog timer is activated.
If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset
signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the
watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a
system reset signal is generated.
The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and
timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer
operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode
for more than 2.5 seconds.
From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog
timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds.
It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every
second.
It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the
counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1 WDVal0}. When going into
the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system
reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always
reads ‘0’.
Table 4.4.1 Watchdog Timer Register RegSysCntl2
Bit Name
Reset
R/W
Description
3
WDReset
0
R/W Reset the Watchdog
1 -> Resets the Logic Watchdog
0 -> No action
The Read value is always '0'
2
SleepEn
0
R/W See Operating modes (sleep)
1
WDVal1
0
R Watchdog timer data Ck[1] divided by 4
0
WDVal0
0
R Watchdog timer data Ck[1] divided by 2
4.5 CPU State after Reset
Reset initializes the CPU as shown in Table 4.5.1 below.
1H
Table 4.5.1 Initial CPU Value after Reset.
Name
Bits
Program counter 0
12
Program counter 1
12
Program counter 2
12
Stack pointer
2
Index register
7
Carry flag
1
Zero flag
1
Halt 1
Instruction register
16
Symbol
PC0
PC1
PC2
SP
IX
CY
Z
HALT
IR
Periphery registers 4 Reg.
Initial Value
hex 000 (as a result of Jump 0)
Undefined
Undefined
PSP[0] selected
Undefined
Undefined
Undefined
0
Jump 0
See peripheral memory map
Copyright © 2005, EM Microelectronic-Marin SA
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| PDF Descargar | [ Datasheet EM6521.PDF ] | |
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