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EM488M3244VBA Schematic ( PDF Datasheet ) - Eorex

Teilenummer EM488M3244VBA
Beschreibung Synchronous DRAM
Hersteller Eorex
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Gesamt 17 Seiten
EM488M3244VBA Datasheet, Funktion
eorexwww.DataSheet4U.com
EM488M3244VBA
256Mb (2M×4Bank×32) Synchronous DRAM
Features
Fully Synchronous to Positive Clock Edge
Single 3.3V ±0.3V Power Supply
LVTTL Compatible with Multiplexed Address
Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
Programmable CAS Latency (C/L) - 2 or 3
Data Mask (DQM) for Read / Write Masking
Programmable Wrap Sequence
Sequential (B/L = 1/2/4/8/full Page)
Interleave (B/L = 1/2/4/8)
Burst Read with Single-bit Write Operation
All Inputs are Sampled at the Rising Edge of
the System Clock
Auto Refresh and Self Refresh
4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM488M3244VBA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages: TFBGA-90B(13mmx8mm).
Ordering Information
Part No
Organization Max. Freq
EM488M3244VBA-75F
8M X 32
133MHz @CL3
Package
Grade Pb
TFBGA -90B Commercial Free
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
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EM488M3244VBA Datasheet, Funktion
eorex
Block Diagram
EM488M3244VBA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
Auto/Self
Refresh Counter
DQM
Memory
Array
S/A & I/O Gating
Col. Decoder
Write DQM
Control
Data In
Data Out
Col. Add. Buffer
Mode Register Set
Col. Add. Counter
Burst Counter
Read DQM
Control
Timing Register
CLK CKE /CS /RAS /CAS /WE DQM
DOi
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6 Page









EM488M3244VBA pdf, datenblatt
eorex
EM488M3244VBA
2. DQM Truth Table
Command
Symbol
CKE
n-1 n
Data Write/Output Enable
Data Mask/Output Disable
ENB
MASK
HX
HX
Upper Byte Write Enable/Output Enable
BSTH
HX
Read
READ
HX
Read with Auto Pre-charge
READA
HX
Write
WRIT
HX
Write with Auto Pre-charge
WRITA
HX
Bank Activate
ACT
HX
Pre-charge Select Bank
PRE
HX
Pre-charge All Banks
PALL
HX
Mode Register Set
MRS
HX
H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
/CS
H
L
L
L
L
L
L
L
L
L
L
3. CKE Truth Table
Item
Activating
Command
Clock Suspend Mode Entry
CKE
Symbol
/CS /RAS /CAS /WE Addr.
n-1 n
HL X X
XX
X
Any
Clock
Suspend
Idle
Clock Suspend Mode
Clock Suspend Mode Exit
CBR Refresh Command
REF
LLX
LHX
HH L
X
X
L
XX
XX
LH
X
X
X
Idle
Self Refresh
Self Refresh Entry
Self Refresh Exit
SELF
HL L
LH L
LHH
L
H
X
LH
HH
XX
X
X
X
Idle Power Down Entry
HLX X
XX
X
Power Down Power Down Exit
LHX X
XX
X
Remark H = High level, L = Low level, X = High or Low level (Don't care)
Jul. 2006
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