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EM4816Mxxxx-xx Schematic ( PDF Datasheet ) - Eorex

Teilenummer EM4816Mxxxx-xx
Beschreibung 64Mb SDRAM
Hersteller Eorex
Logo Eorex Logo 




Gesamt 30 Seiten
EM4816Mxxxx-xx Datasheet, Funktion
www.DataSheet4U.com
64Mb SDRAM
Ordering Information
EM 48 2M 32 4 4 V T A – 5 L
EOREX
Logo
EDO/FPM
D-RAMBUS
DDRSDRAM
DDRSGRAM
SGRAM
SDRAM
: 40
: 41
: 42
: 43
: 46
: 48
Density
16M : 16 Mega Bits
8M : 8 Mega Bits
4M : 4 Mega Bits
2M : 2 Mega Bits
1M : 1 Mega Bit
Organization
8 : x8
9 : x9
16 : x16
18 : x18
32 : x32
Refresh
1 : 1K, 8 : 8K
2 : 2K, 6 :16K
4 : 4K
Bank
2 : 2Bank 6 : 16Bank
4 : 4Bank 3 : 32Bank
8 : 8Bank
Interface
V: 3.3V
R: 2.5V
URL: http://www.eorex.com
Rev.01
F: PB free package
Power
Blank : Standard
L : Low power
I : Industrial
Min Cycle Time ( Max Freq.)
-5 : 5ns ( 200MHz )
-6 : 5ns ( 167MHz )
-7 : 7ns ( 143MHz )
-75 : 7.5ns ( 133MHz )
-8 : 8ns ( 125MHz )
-10 : 10ns ( 100MHz )
Revision
A : 1st B : 2nd
C : 3rd D :4th
G: for VGA version only
Package
C: CSP B: uBGA
T: TSOP Q: TQFP
P: PQFP ( QFP )
L: LQFP
1/33






EM4816Mxxxx-xx Datasheet, Funktion
64Mb SDRAM
Commands
Mode register set command ( /CS, /RAS, / CAS, /WE = Low )
CLK
/CS
/RAS
/CAS
/WE
BA
A10
CKE
Add
‘H’
The EM482M3244VTA have a mode register that
defines how the device operates. In this command, A0
through BA are the data input pins. After power on, the
mode register set command must be executed to
initialize the device. The mode register can be set only
when all banks are in idle state. The EO482M3244VTA,
cannot accept any other commands,only during 2CLK
can following this command.
( Figure. 1 Mode register set command )
Active command ( /CS, /RAS = Low , /CAS, /WE = High )
CLK
/CS
/RAS
/CAS
/WE
BA
A10
CKE
Add
Row
‘H’
Row
The EM482M3244VTA have 4 banks, each with 2,048
rows. This command activates the bank selected by BA
and a row address selected by A0 through A10.This
command corresponds to a conventional DRAM’s /RAS
falling.
( Figure. 2 Row address strobe and bank activate command )
Rev.01
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6 Page









EM4816Mxxxx-xx pdf, datenblatt
Simplified State Diagram
64Mb SDRAM
Mode
Regis ter
Set
MRS
IDLE
Self
Refres h
SELF
SELF
Ex
it
REF
CKE
CKE
CBR
Refres h
Power
Down
Write
WRITE
Sus pend
CKE
CKE
WRITE
Row
Active
CKE
ReaBdSTCKE
Read
Active
Power
Down
Read
Write
READ
CKE
CKE
READ
Sus pend
WRITEA
Sus pend
CKE
CKE
WRITEA
READA
CKE
CKE
READA
Sus pend
POWER
ON
Precharge
Precharge
Manual Input
Automatic Sequence
Rev.01
12/33

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