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ADP3192A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3192A
Beschreibung 8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP3192A Datasheet, Funktion
8-Bit Programmable 2- to 4-Phase
Synchronous Buck Controller
ADP3192A
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
±7.7 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Fast enhanced PWM (FEPWM) flex mode for excellent load
transient performance
Active current balancing between all output phases
Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both
VR10.x and VR11 specifications
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for next generation
Intel® processors
VRM modules
GENERAL DESCRIPTION
The ADP3192A1 is a highly efficient, multiphase, synchronous
buck-switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance Intel processors. It uses an internal 8-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.5 V and 1.6 V.
This device uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and efficiency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
or 4-phase operation, allowing for the construction of up to
four complementary buck-switching stages.
FUNCTIONAL BLOCK DIAGRAM
VCC
31
RT RAMPADJ
12 13
GND 18
SHUNT
REGULATOR
UVLO
SHUTDOWN
850mV –
EN 1
+
DAC
+ 150mV
CSREF
+
+
DAC –
– 350mV
PWRGD 2
DELAY
OSCILLATOR
19 OD
+
CMP
+
CMP
+
CMP
+
CMP
SET EN
RESET
30 PWM1
RESET
29 PWM2
RESET
28 PWM3
2/3/4-PHASE
DRIVER LOGIC 27 PWM4
RESET
CROWBAR
CURRENT
LIMIT
TTSENSE 10
VRHOT 9
VRFAN 8
THERMAL
THROTTLING
CONTROL
25 SW1
24 SW2
23 SW3
22 SW4
ILIMIT 11
DELAY 7
17 CSCOMP
CURRENT
MEASUREMENT
+
15 CSREF
AND LIMIT
16 CSSUM
21 IMON
IREF 20
COMP 5
4 FB
FBRTN 3
PRECISION
REFERENCE
VIDSEL 40
VID DAC
32 33 34 35 36 37 38 39
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
BOOT
VOLTAGE
AND
SOFT START
CONTROL
14 LLSET
6 SS
ADP3192A
Figure 1.
The ADP3192A also includes programmable no load offset and
slope functions to adjust the output voltage as a function of the
load current, optimally positioning it for a system transient. In
addition, the ADP3192A provides accurate and reliable short-
circuit protection, adjustable current limiting, and a delayed
power-good output that accommodates on-the-fly output
voltage changes requested by the CPU.
The ADP3192A has a built-in shunt regulator that allows the part
to be connected to the 12 V system supply through a series resistor.
The ADP3192A is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a
40-lead LFCSP.
1 Protected by U.S. Patent Number 6,683,441; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.






ADP3192A Datasheet, Funktion
ADP3192A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
FBRTN
PWM3 to PWM4, RAMPADJ
SW1 to SW4
<200 ns
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to VCC + 0.3 V
−5 V to +25 V
−10 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
39°C/W
300°C
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages
referenced to GND.
ESD CAUTION
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ADP3192A pdf, datenblatt
ADP3192A
To increase the current in any given phase, enlarge RSW for that
phase (make RSW = 0 for the hottest phase and do not change it
during balancing). Increasing RSW to only 500 Ω makes a substan-
tial increase in phase current. Increase each RSW value by small
amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE
A high gain, high bandwidth, voltage mode error amplifier is
used for the voltage mode control loop. The control input voltage
to the positive input is set via the VID logic according to the
voltages listed in Table 4.
This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
Resistor RB and is used for sensing and controlling the output
voltage at this point. A current source (equal to IREF) from the
FB pin flowing through RB is used for setting the no load offset
voltage from the VID voltage. The no load voltage is negative
with respect to the VID DAC. The main loop compensation is
incorporated into the feedback network between FB and COMP.
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This
reference current sets IFB, IDELAY, ISS, ILIMIT, and ITTSENSE. A resistor
to ground programs the current based on the 1.5 V output.
1.5 V
IREF =
R IREF
Typically, RIREF is set to 100 kΩ to program IREF = 15 μA. The
following currents are then equal to
IFB = IREF = 15 μA
IDELAY = IREF = 15 μA
ISS = IREF = 15 μA
ILIMIT = 2/3 (IREF) = 10 μA
FAST ENHANCED PWM MODE
Fast enhanced PWM mode (FEPWM) is intended to improve
the transient response of the ADP3192A to a load setup. In
previous generations of controllers, when a load step-up
occurred, the controller had to wait until the next turn-on of
the PWM signal to respond to the load change. Enhanced
PWM mode allows the controller to immediately respond when
a load step-up occurs. This allows the phases to respond more
quickly when a load increase takes place.
DELAY TIMER
The delay times for the start-up timing sequence are set with a
capacitor from the DELAY pin to GND. In UVLO, or when EN is
logic low, the DELAY pin is held at GND. After the UVLO and
EN signals are asserted, the first delay time (TD1 in Figure 7) is
initiated. A current flows out of the DELAY pin to charge CDLY.
This current is equal to IREF, which is typically 15 μA. A compara-
tor monitors the DELAY voltage with a threshold of 1.7 V. The
delay time is therefore set by the IREF current charging a capacitor
from 0 V to 1.7 V. This DELAY pin is used for multiple delay
timings (TD1, TD3, and TD5) during the start-up sequence. In
addition, DELAY is used for timing the current-limit latch off,
as explained in the Current-Limit, Short-Circuit, and Latch-Off
Protection section.
SOFT START
The soft start times for the output voltage are set with a
capacitor from the SS pin to GND. After TD1 and the phase
detection cycle are complete, the SS time (TD2 in Figure 7)
starts. The SS pin is disconnected from GND, and the capacitor
is charged up to the 1.1 V boot voltage by the SS amplifier,
which has an output current equal to IREF (typically 15 μA).
The voltage at the FB pin follows the ramping voltage on the
SS pin, limiting the inrush current during startup. The soft start
time depends on the value of the boot voltage and CSS.
Once the SS voltage is within 100 mV of the boot voltage, the
boot voltage delay time (TD3 in Figure 7) is started. The end of
the boot voltage delay time signals the beginning of the second
soft start time (TD4 in Figure 7). The SS voltage now changes
from the boot voltage to the programmed VID DAC voltage
(either higher or lower) using the SS amplifier with the output
current equal to IREF. The voltage of the FB pin follows the
ramping voltage of the SS pin, limiting the inrush current
during the transition from the boot voltage to the final DAC
voltage. The second soft start time depends on the boot voltage,
the programmed VID DAC voltage, and CSS.
Rev. 0 | Page 12 of 32

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