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Teilenummer | W83L603G |
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Beschreibung | (W83L603G / W83L604G) SMBus GPIO Controller | |
Hersteller | Winbond | |
Logo | ||
Gesamt 22 Seiten www.DataSheet4U.com
Winbond
SMBus GPIO Controller
W83L603G
W83L604G
Revision: 1.0 Date: August 2006
W83L603G/W83L604G
4. PIN DESCRIPTION
INts
I/OD12ts
I/O12t
I/O(D)16t
I/O(D)12t
OD12
TTL level Schmitt-trigger input pin
TTL level bi-directional pin open drain output with 12 mA sink capability and schmitt-
trigger level input
TTL level bi-directional pin bi-directional output with 12 mA source-sink capability
TTL level bi-directional pin bi-directional (or open drain) output with 16 mA (source-)
sink capability
TTL level bi-directional pin bi-directional (or open drain) output with 12 mA (source-)
sink capability
Open drain output pin with 12 mA sink capability
4.1 W83L603G
PIN SYMBOL
1 SCL
2 SDA
3 GP10/LED0
4 GP11/LED1
5 GP12/LED2
6 GP13/LED3
7 VSS
8 GP14/BEEP
9 GP15 / A2
10 GP16 / A1
11 GP17 / A0
12 INT#
13 RST#
14 3VDD
I/O
INts
I/OD12ts
I/O(D)16t
I/O(D)16t
I/O(D)16t
I/O(D)16t
PWR
I/O(D)16t
I/O12t
I/O12t
I/O12t
OD12
INts
PWR
FUNCTION
SMBus Clock.
SMBus bi-directional Data.
General Purpose I/O. ; LED output
General Purpose I/O. ; LED output
General Purpose I/O. ; LED output
General Purpose I/O. ; LED output
Power Pin.
General Purpose I/O. ; BEEP output
General Purpose I/O.; Strapping pin for SMBus address bit
2, this pin is internal weak pull down during hardware
reset.
General Purpose I/O.; Strapping pin for SMBus address bit
1, this pin is internal weak pull down during hardware
reset.
General Purpose I/O.; Strapping pin for SMBus address bit
0, this pin is internal weak pull down during hardware
reset.
Auto-generated Interrupt signal when detecting a transition on
GP inputs.
System reset signal input. Low level must be greater than
0.1uS.
Power Pin.
Publication Release Date: August 2006
- 3 - Revision 1.0
6 Page W83L603G/W83L604G
Register 22h – Global configuration register
BIT 7 6 5 4 3 2 1 0
R/W WO RFU RW RW RW RW RW RW
Default
0
0
0
0
0
0
0
0
Bit7: Write “1” to issue a software reset.
Bit6: Reserved for future use.
Bit5: Low power enable bit. The internal clock generator will shutdown while the bit is set. In the low-
power mode, the functions of SMBus, LED, BEEP, and all signals configured as the pulse mode will
NOT work.
Bit4: Wake-up enable. If the bit is set, low-power enable bit (Bit-5) can be cleared whenever interrupt
event is triggered on GPI pin. To enable the interrupt control register (CR06,CR16) is necessary.
Bit3: Interrupt polarity bit. Refer to Section 7.2.2 for INT pin type implementation.
Bit2: This bit configures the INT signal output as level (“0”; by default) or pulse (“1”) style.
Bit1: GP2 registers mask enable. Set “1” will mask the RST# signal for all GP2 registers. (10h ~ 17h)
Bit0: GP1 registers mask enable. Set “1” will mask the RST# signal for all GP1 registers. (00h ~ 08h)
*Bit1 and Bit0 will not be reset by RST#.
Publication Release Date: August 2006
- 9 - Revision 1.0
12 Page | ||
Seiten | Gesamt 22 Seiten | |
PDF Download | [ W83L603G Schematic.PDF ] |
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