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AD9869 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9869
Beschreibung Broadband Modem Mixed-Signal Front End
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9869 Datasheet, Funktion
Broadband Modem Mixed-Signal Front End
AD9869
FEATURES
Low cost 3.3 V CMOS MxFE for broadband modems
12-bit DAC converter
2×/4× interpolation filter
200 MSPS DAC update rate
Integrated 17 dBm line driver with 19.5 dB gain control
12-bit, 80 MSPS, ADC converter
−12 dB to +48 dB low noise RxPGA (<3 nV/√Hz)
Third-order, programmable low-pass filter
Flexible digital data path interface
Half- and full-duplex operation
Pin compatible with the AD9866
Various power-down/reduction modes
Internal clock multiplier (PLL)
2 auxiliary programmable clock outputs
Available in a 64-lead LFCSP_VQ
APPLICATIONS
Broadband wireline networking
GENERAL DESCRIPTION
The AD9869 is a mixed-signal front-end (MxFE®) IC for
transceiver applications requiring Tx path and Rx path
functionality with data rates up to 80 MSPS. A lower cost, pin-
compatible version of the AD9866, the AD9869 removes the
current amplifier (IAMP) IOUTP functionality and limits the
PLL VCO operating range of 80 MHz to 200 MHz.
The part is well suited for half- and full-duplex applications.
The digital interface is extremely flexible, allowing simple
interfacing to digital back ends that support half- or full-duplex
data transfers, often allowing the AD9869 to replace discrete
ADC and DAC solutions. Power-saving modes include the
ability to reduce power consumption of individual functional
blocks or power down unused blocks in half-duplex applications.
A serial port interface (SPI) allows software programming of
the various functional blocks. An on-chip PLL clock multiplier
and synthesizer provide all the required internal clocks, as well
as two external clocks, from a single crystal or clock source.
The Tx signal path consists of a 2×/4× low-pass interpolation
filter, a 12-bit TxDAC, and a line driver. The transmit path
signal bandwidth can be as high as 34 MHz at an input data rate
FUNCTIONAL BLOCK DIAGRAM
PWRDWN
MODE
TXEN/TXSYNC
TXCLK/TXQUIET
ADIO[11:6]/
Tx[5:0]
ADIO[5:0]/
Rx[5:0]
AD9869
2-4X
12
TxDAC
IAMP
0 TO –7.5dB 0 TO –12dB
CLK
SYNC.
2M CLK
MULTIPLIER
IOUTN+
IOUTN–
CLKOUT1
CLKOUT2
OSCIN
XTAL
RXEN/RXSYNC
RXCLK
AGC[5:0]
PORT
SPI
PORT
12
ADC
80MSPS
2-POLE
LPF
1-POLE
LPF
6
0 TO 6dB –6 TO +18dB –6 TO +24dB
4 REGISTER = 1dB = 6dB
= 6dB
CONTROL
Figure 1.
RX+
RX–
of 80 MSPS. The TxDAC provides differential current outputs
that can be steered directly to an external load or to an internal
low distortion current amplifier (IAMP) capable of delivering
17 dBm peak signal power. Tx power can be digitally controlled
over a 19.5 dB range in 0.5 dB steps.
The receive path consists of a programmable amplifier (RxPGA),
a tunable low-pass filter (LPF), and a 12-bit ADC. The low noise
RxPGA has a programmable gain range of −12 dB to +48 dB in
1 dB steps. Its input referred noise is less than 3 nV/√Hz for gain
settings beyond 36 dB. The receive path LPF cutoff frequency
can be set over a 15 MHz to 35 MHz range or it can be simply
bypassed. The 12-bit ADC achieves excellent dynamic performance
up to an 80 MSPS span. Both the RxPGA and the ADC offer
scalable power consumption allowing power/performance
optimization.
The AD9869 provides a highly integrated solution for many
broadband modems. It is available in a space-saving package, a
16-lead LFCSP, and is specified over the commercial temperature
range (−40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.






AD9869 Datasheet, Funktion
AD9869
Parameter
Rx PATH LATENCY2
Full-Duplex Interface
Half-Duplex Interface
Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 50 MSPS3
RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)
Signal-to-Noise and Distortion (SINAD)
Total Harmonic Distortion (THD)
RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)
Signal-to-Noise and Distortion (SINAD)
Total Harmonic Distortion (THD)
Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 80 MSPS4
RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output)
RxPGA Gain = 40 dB
IOUTP± Pins to RX± Pins
RxPGA Gain = 0 dB
IOUTP± Pins to RX± Pins
Temp Test Level1 Min Typ
Full V
Full V
10.5
10.0
25°C III
25°C III
25°C III
25°C III
Full IV
Full IV
43.7
−71
63.1
−67.2
64.3
−67.3
25°C III
25°C III
25°C III
25°C III
25°C II
25°C II
41.8
−67
58.6
−62.9
61.1 62.9
−70.8
25°C III
25°C III
83
123
1 See the Explanation of Test Levels section.
2 Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC.
3 fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 15.5 MHz with Register 0x08 = 0x80.
4 fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 26 MHz with Register 0x08 = 0x80.
Max Unit
Cycles
Cycles
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−60.8 dBc
dBc
dBc
Rev. A | Page 5 of 36

6 Page









AD9869 pdf, datenblatt
Pin No.
15
16
Mnemonic
TXCLK
TXQUIET
RXCLK
17, 64
18, 63
19
20
21
22
23
24
25 to 29
30
31, 34, 36, 39, 44, 47, 48
32, 33
35, 40, 43
37, 38
41
42
45, 49
46
50
51
52
53
54
55
56
57
58
59
60
61
62
DRVDD
DRVSS
CLKOUT1
SDIO
SDO
SCLK
SEN
GAIN
PGA[5]
PGA[4:0]
RESET
AVSS
REFB, REFT
AVDD
RX−, RX+
REFADJ
REFIO
NC
IOUTN−
IOUTN+
IOUTP−
IOUTP+
MODE
CONFIG
CLKVSS
XTAL
OSCIN
CLKVDD
DVSS
DVDD
CLKOUT2
PWRDWN
EPAD
1 HD = half-duplex mode; FD = full-duplex mode.
Mode 1
HD
FD
HD
FD
FD
HD or FD
HD or FD
AD9869
Description
ADIO Sample Clock Input.
Fast TxDAC/IAMP Power-Down.
ADIO Request Clock Input.
Rx and Tx Clock Output at 2 x fADC.
Digital Output Driver Supply Input.
Digital Output Driver Supply Return.
fADC/N Clock Output (R = 1, 2, or 3).
Serial Port Data Input/Output.
Serial Port Data Output.
Serial Port Clock Input.
Serial Port Enable Input.
Tx Data Port (Tx[5:0]) Mode Select.
MSB of PGA Input Data Port.
Bit 4 to Bit 0 of PGA Input Data Port.
Reset Input (Active Low).
Analog Supply Return.
ADC Reference Decoupling Nodes.
Analog Power Supply Input.
Receive Path − and + Analog Inputs.
TxDAC Full-Scale Current Adjust.
TxDAC Reference Input/Output.
Do Not Connect; Leave Open.
−Tx Mirror Current Output Sink.
+Tx Mirror Current Output Sink.
−TxDAC Current Output Source.
+TxDAC Current Output Source.
Digital Interface Mode Select Input, Low = HD, High = FD.
Power-Up SPI Register Default Setting Input.
Clock Oscillator/Synthesizer Supply Return.
Crystal Oscillator Inverter Output.
Crystal Oscillator Inverter Input.
Clock Oscillator/Synthesizer Supply.
Digital Supply Return.
Digital Supply Input.
fOSCIN/L Clock Output (L = 1, 2, or 4).
Power-Down Input.
The exposed pad must be soldered to ground.
Rev. A | Page 11 of 36

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