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PDF 33879 Data sheet ( Hoja de datos )
| Número de pieza | 33879 | |
| Descripción | Configurable Octal Serial Switch | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Advance Information
Document Number: MC33879
Rev 6.0, 6/2007
Configurable Octal Serial Switch
with Open Load Detect Current
Disable
33879
33879A
The 33879 device is an 8-output hardware-configurable, high-side/
low-side switch with 16-bit serial input control. Two of the outputs may
be controlled directly via microprocessor for PWM applications. The
33879 incorporates SMARTMOS technology, with CMOS logic,
bipolar/MOS analog circuitry, and DMOS power MOSFETs. The 33879
controls various inductive, incandescent, or LED loads by directly
interfacing with a microcontroller. The circuit’s innovative monitoring
and protection features include very low standby currents, cascade
fault reporting, internal +45 V clamp voltage for low-side configuration,
-20 V high-side configuration, output-specific diagnostics, and
independent overtemperature protection.
HIGH SIDE/ LOW SIDE SWITCH
Features
www.DataSheet4U.com
• Designed to Operate 5.5 V < VPWR < 26.5 V
• 16-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V
Compatible
• Outputs Are Current Limited (0.6 A to 1.2 A) to Drive
Incandescent Lamps
• Output Voltage Clamp, +45 V (Low Side) and -20 V (High Side)
During Inductive Switching
• On/Off Control of Open Load Detect Current (LED Application)
• Internal Reverse Battery Protection on VPWR
• Loss of Ground or Supply Will Not Energize Loads or Damage IC
• Maximum 5.0 µA IPWR Standby Current at 13 V VPWR
• RDS(ON) of 0.75 Ω at 25°C Typical
• Short Circuit Detect and Current Limit with Automatic Retry
• Independent Overtemperature Protection
• Pb-Free Packaging Designated by Suffix Code EK
DWB SUFFIX EXPOSED PAD
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33879EK/R2
MCZ33879EK/R2
MCZ33879AEK/R2
-40°C to 125°C
32 SOICW-EP
MCU
A0
MOSI
SCLK
CS
MISO
PWM1
PWM2
VPWR
+5.0 V
33879
VDD VPWR
EN
DI
SCLK
CS
DO
D1
D2
D3
D4
S1
S2
S3
S4
IN5
D5
IN6 D6
D7
D8
S5
GND S6
S7
S8
VBAT
M
High-Side Drive
H-Bridge Configuration
VBAT VBAT
Low-Side Drive
Figure 1. 33879 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
PIN CONNECTIONS
Table 2. 33879 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number Pin Name
23 S3
26 D4
27 S4
28 D7
29 S7
31 VPWR
32 DO
33 EP
Pin
Function
Output
Output
Output
Output
Output
Input
Output
Ground
Formal Name
Source Output 3
Drain Output 4
Source Output 4
Drain Output 7
Source Output 7
Battery Input
Serial Data Output
Exposed Pad
Definition
Output 3 MOSFET source pin.
Output 4 MOSFET drain pin.
Output 4 MOSFET source pin.
Output 7 MOSFET drain pin.
Output 7 MOSFET source pin.
Power supply pin to the 33879. VPWR has internal reverse battery
protection.
SPI control data output pin from the 33879 to the MCU. DO=0 no fault,
DO=1 specific output has fault.
Device will perform as specified with the Exposed Pad un-terminated
(floating) however, it is recommended that the Exposed Pad be terminated
to pin 1 (GND) and system ground.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33879
5
5 Page 
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted.
Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.
Characteristic
Symbol
Min
Typ
Max Unit
DIGITAL INTERFACE TIMING (14)
Recommended Frequency of SPI Operation (14)
fSPI – 4.0 – MHz
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
t LEAD
100
–
– ns
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
t LAG
50
–
– ns
DI to Falling Edge of SCLK (Required Setup Time)
t DI (SU)
16
–
– ns
Falling Edge of SCLK to DI (Required Hold Time)
DI, CS, SCLK Signal Rise Time (15)
t DI (HOLD)
20
–
– ns
t R(DI)
–
5.0
–
ns
DI, CS, SCLK Signal Fall Time (15)
t F(DI)
–
5.0
–
ns
Time from Falling Edge of CS to DO Low Impedance (16)
t DO (EN)
–
– 55 ns
Time from Rising Edge of CS to DO High Impedance (17)
t DO (DIS)
–
– 55 ns
Time from Rising Edge of SCLK to DO Data Valid (18)
t VALID
–
25 55 ns
Notes
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin.
18. Time required to obtain valid data out from DO following the rise of SCLK.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33879
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet 33879.PDF ] | |
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