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W215B Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer W215B
Beschreibung Notebook PC system Frequency Generator
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 14 Seiten
W215B Datasheet, Funktion
PRELIMINARY
W215B
Notebook PC System Frequency Generator for K6 Processors
Features
• Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, USB plus 14.318 MHz (REF0:1)
• MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)
• Two fixed outputs separately selectable as 24-MHz or
48-MHz (default = 48-MHz)
• VDDQ3 = 3.3V±5%, VDDQ2 = 3.3V±5%
• Uses external 14.318-MHz crystal
• Available in 48-pin TSSOP (6.1-mm)
10CPU output impedance
Table 1. Pin Selectable Frequency
95/100_SEL
CPU, SDRAM
Clocks (MHz)
0 95.0
1 100.0
PCI Clocks
CPU/3
CPU/3
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
www.DataSheet4U.com
CPU_2.5#
MODE
I/O
Control
Stop
Output
Control
95/100_SEL
PLL 1
PWR_DWN#
Stop
Output
Control
Power
Down
Control
PLL2
VDDQ3
REF0
REF1
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
CPU2
CPU3
VDDQ3
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
Pin Configuration
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
GND
95/100_SEL
Reserved
Reserved
VDDQ3
48/24MHZ
48/24MHZ
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SDRAM5
SDRAM6/CPUSTOP#
SDRAM7/PCISTOP#
PCI_F
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
48/24MHZ
48/24MHZ
48 VDDQ3
47 CPU_2.5#
46 VDDQ2
45 IOAPIC
44 PWR_DWN#
43 GND
42 CPU0
41 CPU1
40 VDDQ2
39 CPU2
38 CPU3
37 GND
36 SDRAM0
35 SDRAM1
34 VDDQ3
33 SDRAM2
32 SDRAM3
31 GND
30 SDRAM4
29 SDRAM5
28 VDDQ3
27 SDRAM6/CPU_STOP#
26 SDRAM7/PCI_STOP#
25 VDDQ3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07222 Rev. *A*
Revised December 15, 2002






W215B Datasheet, Funktion
PRELIMINARY
W215B
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
tP Period
f Frequency, Actual
Measured on rising edge at 1.5V
Determined by PLL divider ratio
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
tSK Output Skew
Measured on rising edge at 1.5V
tSK CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
fST Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
CPU = 100 MHz
Min. Typ. Max.
10
100
14
14
45 50 55
500
100
1.5
3
16
Unit
ns
MHz
V/ns
V/ns
%
ps
ps
ns
ms
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
www.DataSheet4U.com
tP
f
Period
Frequency, Actual
tH High Time
tL Low Time
tR Output Rise Edge Rate
tF Output Fall Edge Rate
tD Duty Cycle
tJC Jitter, Cycle-to-Cycle
tSK Output Skew
tO CPU to PCI Clock Skew
fST Frequency Stabilization
from Power-up (cold
start)
Zo AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
CPU = 100 MHz
Min. Typ. Max.
30
33.3
12
12
14
14
45 50 55
500
250
14
3
15
Unit
ns
MHz
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Document #: 38-07222 Rev. *A*
Page 6 of 14

6 Page









W215B pdf, datenblatt
PRELIMINARY
Layout Example
+3.3V Supply
FB
0.005 µF
C4
G
VDDQ3
10 µF
C3
G
G
www.DataSheet4U.com
G
VDDQ3
5
C5 G G C6
1G
2
3
4
5G
6
7V
8G
9
10 G
11
12
13
14 G
15 V
16 G
17
18
19
20 G
21
22
23
24 G
+2.5V Supply
VDDQ2
FB
10 µF
C1
G
0.005 µF
C2
G
G 48
47
V 46
G 45
44
43
42
G 41
V 40
G 39
38
37
36
G 35
34VDDQ3
V
Core
G 33
32
G 31
30
G 29
V 28
G 27
26
G V 25
G
G
G
G
G
W215B
FB = Dale ILB1206 - 300 (300@ 100 MHz)
C1 & C3 = 1022 µF C2 & C4 = 0.005 µF C5 = 47 µF C6 = 0.1 µF
G = VIA to GND plane layer V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Document #: 38-07222 Rev. *A*
Page 12 of 14

12 Page





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