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PDF ADC121S625 Data sheet ( Hoja de datos )
| Número de pieza | ADC121S625 | |
| Descripción | Micro Power Sampling A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2005
www.DataSheet4U.com
ADC121S625
12-Bit, 50 ksps to 200 ksps, Differential Input, Micro
Power Sampling A/D Converter
General Description
The ADC121S625 is a 12-bit, 50 ksps to 200 ksps sampling
Analog-to-Digital (A/D) converter that features a fully differ-
ential, high impedance analog input and an external refer-
ence. While best performance is achieved with reference
voltage between 500mV and 2.5V, the reference voltage can
be varied from 100mV to 2.5V, with a corresponding resolu-
tion between 49µV and 1.22mV.
The output serial data is binary 2’s complement, and is
compatible with several standards, such as SPI™, QSPI™,
MICROWIRE™, and with many common DSP serial inter-
faces. The differential input, low power, automatic power
down, and small size make the ADC121S625 ideal for direct
connection to transducers in battery operated systems or
remote data acquisition applications.
Operating from a single +5V supply, the normal power con-
sumption is reduced to a few nanowatts in the power-down
mode. The ADC121S625 is a pin-compatible superior re-
placement for the ADS7817 and is available in the MSOP-8
package. Operation is guaranteed over the industrial tem-
perature range of −40˚C to +85˚C and clock rates of 800 kHz
to 3.2 MHz.
Features
n True Differential Inputs
n Guaranteed performance from 50ksps to 200ksps
n External Reference
n High AC Common-Mode Rejection
n SPI™/QSPI™/MICROWIRE™/DSP compatible Serial
Interface
Key Specifications
n Conversion Rate
n Offset Error
n Gain Error
n INL
n DNL
n CMRR
n Power Consumption
— Active, 200ksps
— Active, 50ksps
— Power Down
50 to 200 ksps
0.4 LSB (typ)
0.05 LSB (typ)
± 1 LSB (max)
± 0.75 LSB (max)
82 dB (typ)
2.25 mW (typ)
1.33 mW (typ)
60 nW (typ)
Applications
n Automotive Navigation
n Portable Systems
n Medical Instruments
n Instrumentation and Control Systems
n Motor Control
n Direct Sensor Interface
Connection Diagram
20132705
Ordering Information
Order Code
ADC121S625CIMM
ADC121S625CIMMX
ADC121S625EVAL
Temperature Range
−40˚C to +85˚C
−40˚C to +85˚C
Description
8-Lead MSOP Package, 1000 Units Tape & Reel
8-Lead MSOP Package, 3500 Units Tape & Reel
Evaluation Board
Top Mark
X0AC
X0AC
TRI-STATE® is a trademark of National Semiconductor Corporation.
MICROWIRE™ is a trademark of National Semiconductor Corporation.
QSPI™ and SPI™ are trademarks of Motorola, Inc.
© 2005 National Semiconductor Corporation DS201327
www.national.com
1 page  
ADC121S625 Converter Electrical Characteristics (Note 8) (Continued)
The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 to 3.2 MHz, fIN = 20 kHz, CL = 100 pF, un-
less otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical Limits
Units
(Note 7)
POWER SUPPLY CHARACTERISTICS
PSRR Power Supply Rejection Ratio
AC ELECTRICAL CHARACTERISTICS
Offset Change with 1.0V change in
VA
Gain Error Change with 1.0V change
in VA
71
83
dB
dB
fSCLK
fSCLK
fS
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate
tACQ
Track/Hold Acquisition Time
4.8 3.2 MHz (min)
200 800 kHz (max)
300 200 ksps (min)
SCLK cycles
1.5
(min)
SCLK cycles
2.0
(max)
tCONV
Conversion Time
Normal Operation
12 12 SCLK cycles
16 SCLK cycles
tCYC
Throughput Time
Short Cycled
SCLK cycles
14
(min)
fRATE
tAD
Throughput Rate
Aperture Delay
200 ksps (max)
6 ns
ADC121S625 Timing Specifications (Note 8)
The following specifications apply for VA = +4.5V to 5.5V, VREF = 2.5V, fSCLK = 0.8 MHz to 3.2 MHz, CL = 100 pF, Boldface
limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Units
tCFCS
tCSCR
tCHLD
tCDV
tDIS
tEN
tCH
tCL
tr
tf
SCLK Fall toCS Fall
CS Fall to SCLK Rise
SCLK Fall to Data Change Hold Time
SCLK Fall to Next DOUT Valid
Rising Edge of CS To DOUT Disabled
2nd SCLK Fall after CS Fall to DOUT Enabled
SCLK High Time
SCLK Low Time
DOUT Rise Time
DOUT Fall Time
(Note 9)
(Note 9)
0 ns (min)
0 ns (min)
10 ns (min)
38 100 ns (max)
38 50 ns (max)
6 50 ns (max)
42 60 ns (min)
42 60 ns (min)
5 50 ns (max)
13 50 ns (max)
Note 1: Absolute maximum ratings are limiting values which indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions
for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not
operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA or VD), the current at that pin should be limited to 10 mA.
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values
for maximum power dissipation listed above will be reached only when the ADC121S625 is operated in a severe fault condition (e.g. when input or output pins are
driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Clock should be in low when CS is asserted, as indicated by the tCSCR and tCFCS specifications.
Note 10: While the maximum sample rate is fSCLK/16, the actual sample rate may be lower than this by having the CS rate being slower than fSCLK/16.
5 www.national.com
5 Page 
Typical Performance Characteristics TA = +25˚C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, fIN = 20 kHz
unless otherwise stated. (Continued)
SINAD vs. VREF
SFDR vs. VREF
20132737
SNR vs. CLOCK FREQUENCY
20132738
THD vs. CLOCK FREQUENCY
20132739
SINAD vs. CLOCK FREQUENCY
20132740
SFDR vs. CLOCK FREQUENCY
20132741
11
20132742
www.national.com
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADC121S625.PDF ] | |
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