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PDF ADC121S051 Data sheet ( Hoja de datos )
| Número de pieza | ADC121S051 | |
| Descripción | 8-Bit A/D Converter | |
| Fabricantes | National Semiconductor | |
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April 2005
ADC081S051
Single Channel, 500 kSPS, 8-Bit A/D Converter
General Description
The ADC081S051 is a low-power, single channel CMOS
8-bit analog-to-digital converter with a high-speed serial in-
terface. Unlike the conventional practice of specifying per-
formance at a single sample rate only, the ADC081S051 is
fully specified over a sample rate range of 200 kSPS to 500
kSPS. The converter is based on a successive-
approximation register architecture with an internal track-
and-hold circuit.
The output serial data is straight binary, and is compatible
with several standards, such as SPI™, QSPI™,
MICROWIRE, and many common DSP serial interfaces.
The ADC081S051 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption
using a +3V or +5V supply is 2.9 mW and 10.5 mW, respec-
tively. The power-down feature reduces the power consump-
tion to as low as 2.6 µW using a +5V supply.
The ADC081S051 is packaged in an 6-lead LLP package.
Operation over the industrial temperature range of −40˚C to
+85˚C is guaranteed.
Features
n Specified over a range of sample rates.
n 6-lead LLP package
n Variable power management
n Single power supply with 2.7V - 5.25V range
n SPI™/QSPI™/MICROWIRE/DSP compatible
Key Specifications
n DNL
n INL
n SNR
n Power Consumption
— 3V Supply
— 5V Supply
+ 0.07 / −0.06 LSB (typ)
+ 0.06 / −0.07 LSB (typ)
49.6 dB (typ)
2.9 mW (typ)
10.5 mW (typ)
Applications
n Portable Systems
n Remote Data Aquisitions
n Instrumentation and Control Systems
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Pin-Compatible Alternatives by Resolution and Speed
All devices are fully pin and function compatible.
Resolution
Specified for Sample Rate Range of:
50 to 200 kSPS
200 to 500 kSPS
500 kSPS to 1 MSPS
12-bit
ADC121S021
ADC121S051
ADC121S101
10-bit
ADC101S021
ADC101S051
ADC081S101
8-bit
ADC081S021
ADC081S051
ADC081S101
Connection Diagram
Ordering Information
Order Code
ADC081S051CISD
ADC081S051CISDX
Temperature Range
−40˚C to +85˚C
−40˚C to +85˚C
20145505
Description
6-Lead LLP Package
6-Lead LLP Package, Tape & Reel
Top Mark
X6C
X6C
TRI-STATE® is a trademark of National Semiconductor Corporation
QSPI™ and SPI™ are trademarks of Motorola, Inc.
© 2005 National Semiconductor Corporation DS201455
www.national.com
1 page  
ADC081S051 Converter Electrical Characteristics (Note 9) (Continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz,
fSAMPLE = 200 kSPS to 500 kSPS, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA =
25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 9)
Units
AC ELECTRICAL CHARACTERISTICS
tQUIET
tAD
tAJ
(Note 10)
Aperture Delay
Aperture Jitter
50 ns (min)
3 ns
30 ps
ADC081S051 Timing Specifications
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz,
fSAMPLE = 200 kSPS to 500 kSPS, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
tCS Minimum CS Pulse Width
tSU CS to SCLK Setup Time
Delay from CS Until SDATA TRI-STATE®
tEN Disabled (Note 11)
10
10
20
tACC
tCL
tCH
tH
tDIS
Data Access Time after SCLK Falling Edge
(Note 12)
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High
Impedance (Note 13)
VA = +2.7 to +3.6
VA = +4.75 to +5.25
VA = +2.7 to +3.6
VA = +4.75 to +5.25
VA = +2.7 to +3.6
VA = +4.75 to +5.25
40
20
0.4 x
tSCLK
0.4 x
tSCLK
7
5
25
6
25
5
tPOWER-UP Power-Up Time from Full Power-Down
1
Units
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the VA pin. The current into the VA pin is limited by the Analog Supply Voltage specification.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10: Minimum Quiet Time required by Bus relinquish and start of the next conversion.
Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.
Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
Note 13: tDIS is derived from the time taken by the output to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted
to remove the effects of charging or discharging the 25 pF capacitor. This means that tDIS is the true bus relinquish time, independent of the bus loading.
5 www.national.com
5 Page 
Applications Information (Continued)
5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC081S051’s input
channels is shown in Figure 7. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should any
input go beyond (VA + 300 mV) or (GND − 300 mV), as these
ESD diodes will begin conducting, which could result in
erratic operation.
The capacitor C1 in Figure 7 has a typical value of 4 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500 ohms. Capacitor C2 is the ADC081S051 sam-
pling capacitor and is typically 26 pF. The ADC081S051 will
deliver best performance when driven by a low-impedance
source to eliminate distortion caused by the charging of the
sampling capacitance. This is especially important when
using the ADC081S051 to sample AC signals. Also important
when sampling dynamic signals is a band-pass or low-pass
filter to reduce harmonics and noise, improving dynamic
performance.
20145514
FIGURE 7. Equivalent Input Circuit
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC081S051 digital inputs (SCLK and CS) are not
limited by the same absolute maximum ratings as the analog
inputs. The digital input pins are instead limited to +6.5V with
respect to GND, regardless of VA, the supply voltage. This
allows the ADC081S051 to be interfaced with a wide range
of logic levels, independent of the supply voltage.
7.0 MODES OF OPERATION
The ADC081S051 has two possible modes of operation:
normal mode, and shutdown mode. The ADC081S051 en-
ters normal mode (and a conversion process is begun) when
CS is pulled low. The device will enter shutdown mode if CS
is pulled high before the tenth falling edge of SCLK after CS
is pulled low, or will stay in normal mode if CS remains low.
Once in shutdown mode, the device will stay there until CS is
brought low again. By varying the ratio of time spent in the
normal and shutdown modes, a system may trade-off
throughput for power consumption.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC081S051 in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode con-
tinuously, CS must be kept low until after the 10th falling
edge of SCLK after the start of a conversion (remember that
a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before
the 16th falling edge, the device will remain in normal mode,
but the current conversion will be aborted, and SDATA will
return to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after tQUIET has
elapsed, by bringing CS low again.
7.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do
not sample continuously, or it is acceptable to trade through-
put for power consumption. When the ADC081S051 is in
shutdown mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted
by bringing CS back high anytime between the second and
tenth falling edges of SCLK, as shown in Figure 8. Once CS
has been brought high in this manner, the device will enter
shutdown mode; the current conversion will be aborted and
SDATA will enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
FIGURE 8. Entering Shutdown Mode
11
20145516
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| PDF Descargar | [ Datasheet ADC121S051.PDF ] | |
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