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PDF DP83850C Data sheet ( Hoja de datos )
| Número de pieza | DP83850C | |
| Descripción | 100 Mb/s TX/T4 Repeater Interface Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1998
DP83850C 100 Mb/s TX/T4 Repeater Interface Controller
(100RIC™)
www.DataSheet4U.com
General Description
Features
The DP83850C 100 Mb/s TX/T4 Repeater Interface Con-
troller, known as 100RIC, is designed specifically to meet
the needs of today's high speed Ethernet networking sys-
tems. The DP83850C is fully compatible with the IEEE
802.3 repeater's clause 27.
The DP83850C supports up to twelve 100 Mb/s links with
its network interface ports. The 100RIC can be configured
to be used with either 100BASE-TX or 100BASE-T4 PHY
technologies. Larger repeaters with up to 372 ports may
be constructed by cascading DP83850Cs together using
the built-in Inter Repeater bus.
In conjunction with a DP83856 100 Mb/s Repeater Infor-
mation Base device, a DP83850C based repeater
becomes a managed entity that is compatible with IEEE
802.3u (clause 30), collecting and providing an easy inter-
face to all the required network statistics.
s IEEE 802.3u repeater and management compatible
s Supports Class II TX translational repeater and Class I
T4 repeater
s Supports 12 network connections (ports)
s Up to 31 repeater chips cascadable for larger hub appli-
cations (up to 372 ports)
s Separate jabber and partition state machines for each
port
s Management interface to DP83856 allows all repeater
MIBs to be maintained
s Large per-port management counters - reduces man-
agement CPU overhead
s On-chip elasticity buffer for PHY signal re-timing to the
DP83850C clock source
s Serial register interface - reduces cost
s Physical layer device control/status access available via
the serial register interface
s Detects repeater identification errors
s 132 pin PQFP package
System Diagram
DP83850C
100 Mb/s
Repeater Interface Controller
(100RIC8)
DP83856
100 Mb/s
Repeater Information Base
(100RIB)
Inter Repeater Bus
Management Bus
RX Enable [11..0]
MII
DP83840A
100 PHY
#0
100Mb/s
Ethernet
Ports
DP83223
100BASE-X
Transceiver
Port 0
DP83840A
100 PHY
#1
DP83223
100BASE-X
Transceiver
Port 1
DP83840A
100 PHY
#2
DP83223
100BASE-X
Transceiver
Port 2
(IR_COL, IR_DV)
DP83840A
100 PHY
#11
DP83223
100BASE-X
Transceiver
Port 11
Statistics
SRAM
Management
CPU
Program
Memory
Management
I/O Devices
Note: The above system diagram depicts the repeater configured in 100BASE-TX mode.
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
100RIC™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
www.national.com
1 page  
1.0 Pin Connection Diagram (Continued)
1.1 Pin Table
Pin Name
/ACTIVEO
/IR_ACTIVE
/IR_BUS_EN
/IR_COL_IN
/IR_COL_OUT
/IRD_ER
/IRD_V
/M_DV
/M_ER
/RST
/SDV
BRDC
CRS[11:0]
EE_CK
EE_CS
EE_DI
EE_DO
GND
GRDIO
IR_VECT[4:0]
IRD[3:0]
IRD_CK
IRD_ODIR
LCK
M_CK
MD[3:0]
MODE[1:0]
PART[5:0]
RDC
RDIO
RDIR
RID[4:0]
RID_ER
RSM[2:0]
RSM[3]/ RXECONFIG
RX_DV
RX_ER
RXC
RXD[3:0]
RXE[11:0]
TX_ER
TX_RDY
TXD[3:0]
TXE[11:0]
VCC
Pin No.
110
132
113
130
131
19
15
116
114
103
109
104
41-30
79
78
81
80
1, 8, 16, 28, 46, 56, 66,76, 85, 94, 101, 111, 117,123
105
125-129
14-11
10
18
100
115
119-122
83-82
84, 87-91
106
107
108
93, 96-99
92
74-72
20
25
26
27
24-21
55-48, 45-42
7
75
3-6
71-68, 65-58
2, 9, 17, 29, 47, 57, 67, 77, 86, 95, 102, 112, 118, 124
5
Section
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.4
2.2
2.4
2.1
2.3
2.3
2.3
2.3
N/A
2.4
2.2
2.2
2.2
2.4
2.4
2.2
2.2
2.4
2.4
2.2
2.2
2.4
2.4
2.4
2.4
2.4
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
N/A
www.national.com
5 Page 
3.0 Functional Description (Continued)
3.6 Jabber Protection State Machine
The jabber specification for 100BASE-T is functionally dif-
ferent than 10BASE-T.
In 10BASE-T, each port's Jabber Protect State machine
ensures that Jabber transmissions are stopped after 5ms
and followed by 96 to 116 bit times silence before the port
is re-enabled.
In 100BASE-T, when a port jabbers, its receive and trans-
mit ports are cutoff until the jabber activity ceases. All other
ports remain unaffected and continue normal operation.
The 100BASE-T Jabber Protect Limit (that is, the time for
which a port can jabber until it is cutoff) for the DP83850C
is reached if the CRS is active for more than 655µs.
A jabbering port that is cut off will be re-enabled when the
jabber activity ceases and the IDLE line condition is
sensed.
3.7 Auto-Partition State Machine
In order to protect the network from a port that is experi-
encing excessive consecutive collisions, each port must
have its own auto-partition state machine.
A port with excessive consecutive collisions will be parti-
tioned after a programmed number of consecutive colli-
sions occur on that port. Transmitting ports will not be
affected.
The DP83850C has a configuration bit that allows the user
to choose how many consecutive collisions a port should
experience before partitioning. This bit can be set for either
32 or 64 consecutive collisions. The IEEE802.3u
100BASE-T standard specifies the consecutive collisions
limit as greater than 60. A partitioned port will be recon-
nected when a collision-free packet of length 512 bits or
more (that is, at least a minimum sized packet) is transmit-
ted out of that port.
The DP83850C also provides a configuration bit that dis-
ables the auto-partition function completely.
3.8 Inter Repeater Bus Interface
The Inter Repeater bus is used to connect multiple
DP83850Cs together to form a logical repeater unit and
also to allow a managed entity. The IR bus allows received
data packets to be transferred from the receiving
DP83850C to the other DP83850Cs in the system. These
DP83850Cs then send the data stream to their transmit
enabled ports.
s Inter Repeater Data Outward Direction. This pin indi-
cates the direction of the data flow with respect to the
DP83850C. When the DP83850C is driving the IR bus
(i.e. it contains port N) this signal is HIGH and when the
DP83850C is receiving data from other DP83850Cs
over the IR bus this signal is LOW.
s Inter Repeater Bus Enable. This signal (connected to
the /ENABLE pin of the external transceivers on the IR
bus) is used in conjunction with the IRD_ODIR signal
(connected to the DIR pin of the transceivers) to TRI-
STATE these transceivers during the change of direction
from input to output, or vice versa. This signal is always
active allowing the IR bus signals to pass through the
transceivers into or out of the 100RIC. However when
the 100RIC switches from input mode (IRD_ODIR=0) to
output mode (IRD_ODIR=1), the /IR_BUS_EN signal is
deasserted allowing the transceivers to TRI-STATE dur-
ing the direction change. After this turn-around, this
signal is asserted back again. (IRD_ODIR assertion
(high) to /IR_BUS_EN low timing is a minimum of 0.1 ns.
and a maximum of 1.0. The time from /IR_BUS_EN
(high) to the IRD_ODIR high is a minimum of 10 ns. and
a maximum of 20 ns. In addition, /ACTIVEO assertion
(low) to /IR_BUS_EN high timing is a maximum of 1.0
ns.)
s Inter Repeater Activity. When there is network activity
the DP83850C asserts this output signal.
s Inter Repeater Collision Output. If there are multiple re-
ceptions on ports of a DP83850C or if the DP83850C
senses concurrent activity on another DP83850C it as-
serts this output.
s Inter Repeater Collision Input. This input indicates that
one of the cascaded DP83850Cs is experiencing a colli-
sion.
s Inter Repeater Vector. When there is reception on a port
the DP83850C drives a unique vector onto these lines.
The vector on the IR bus is compared with the Repeater
ID (RID). The DP83850C will continue to drive the IR
bus if both the vector and RID match.
The following figure shows the conditions that cause an
open collector vector signal to be asserted on the back-
plane bus.
RID[n]=0
&
/ACTIVEO=0
Notification of collisions to other cascaded DP83850Cs is
as important as data transfer across the network. The arbi-
tration logic asynchronously determines if more than one
100RIC, cascaded together, are receiving simultaneously.
The IR bus has a set of status lines capable of conveying
collision information between DP83850Cs to ensure their
main state machines operate in the appropriate manner.
The IR bus consists of the following signals:
s Inter Repeater Data. This is the transfer data, in nibble
format, from the active DP83850C to all other cascaded
DP83850Cs.
s Inter Repeater Data Error. This signal carries the re-
ceive error status from the physical layer in real-time.
s Inter Repeater Data Valid. This signal is used to frame
good packets.
s Inter Repeater Data Clock. All IR data is synchronized
to this clock.
/IR_VECT[n]
Figure 1. Open Collector /IR_VECT[n]
As seen, if the RID[n]=1, and the repeater is receiving on a
port, then the /IR_VECT[n] value would be 1 due to the
pull-up on this pin. In the case that RID[n]=0, then a zero is
driven out on the /IR_VECT[n] signal.
As an example assume that two repeaters with RIDs equal
to RID #1=00010 and RID #2=00011 are connected
through the Inter-RIC bus. The following diagrams depict
the values of /IR_VECT signals over the backplane.
s Active Output. This signal is asserted by a DP83850C
when at least one of its ports is active. It is used to enable
external bus transceivers.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP83850C.PDF ] | |
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