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DP83821 Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer DP83821
Beschreibung 10/100/1000 Mb/s PCI Ethernet Network Interface Controller
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 70 Seiten
DP83821 Datasheet, Funktion
PRELIMINARY
February 2001
DP83821 10/100/1000 Mb/s PCI Ethernet Network Interface
Controller
www.DataSheet4U.com
General Description
DP83821 is a single-chip 10/100/1000 Mb/s Ethernet
Controller for the PCI bus. It is targeted at high-
performance adapter cards and mother boards. The
DP83821 fully implements the V2.2 33 MHz, 32-bit PCI bus
interface for host communications with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83821 can support full duplex 10/100/1000 Mb/s
transmission and reception.
Features
— IEEE 802.3 Compliant, 33 Mhz, 32-bit PCI V2.2
MAC/BIU supports data rates from 1 Mb/s to 1000 Mb/s.
This allows support for traditional 10 Mb/s Ethernet, 100
Mb/s Fast Ethernet, as well as 1000 Mb/s Gigabit
Ethernet.
— Flexible, programmable Bus master - burst sizes of up to
256 dwords (1024 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design
Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,
PCI Power Management Specification v1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, and OnNow, including directed packets, Magic
Packet with SecureOn, ARP packets, pattern match
packets, and Phy status change
— GMII/MII provides IEEE 802.3 standard interface to
support 10/100/1000 Mb/s physical layer devices
— Ten-Bit Interface (TBI) for support of 1000BASE-X
— Virtual LAN (VLAN) and long frame support. VLAN tag
insertion support for transmit packets. VLAN tag
detection and removal for receive packets
— 802.3x Full duplex flow control, including automatic
transmission of Pause frames based on Rx FIFO
thresholds
— IPv.4 checksum task off-loading. Supports checksum
generation and verification of IP, TCP, and UDP headers
— 802.1D and 802.1Q priority queueing support. Supports
multiple priority queues in both transmit and receive
directions.
— Extremely flexible Rx packet filtration including: single
address perfect filter with MSb masking, broadcast,
2,048 entry multicast/unicast hash table, deep packet
pattern matching for up to 4 unique patterns.
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management.
— Internal 8 KB Transmit and 32 KB Receive data FIFOs
— Supports Jumbo packets
— Serial EEPROM port with auto-load of configuration data
from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Full Duplex support for 10/100/1000 Mb/s data rates
— 208-pin PQFP package
— Low power CMOS design
— 3.3V powered I/Os with 5V tolerant inputs
— JTAG Boundary Scan supported
System Diagram
PCI Bus
DP83821
M II
GM II
10/100/1000 M b/s
PHY
EE PR O M (optional)
Boot R O M (optional)
© 2001 National Semiconductor Corporation
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DP83821 Datasheet, Funktion
2.0 Pin Descriptions (Continued)
Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).
Symbol
TXER/TXD9
GTXCLK/
TXPMACLK
REF125
Pin No(s)
154
140
137
Direction
O
O
I
Description
Transmit Error: This signal is synchronous to TXCLK and provides error
indications and also is used for 1000 Mb/s half-duplex carrier extension and
packet bursting functions. The DP83821 will only assert this signal in 1000 Mb/s
mode of operation.
TBI Transmit Data: In TBI mode, this is TXD9 of the 10-bit TBI Transmit data.
GMII transmit Clock: A continuous clock used for 1000 Mb/s. It is output to an
external PMD and is the reference clock for Transmit GMII signaling. The clock
frequency is 125 MHz.
TBI Transmit Clock: In TBI mode, this is the 125MHz transmit clock to an
external PMD and is the reference for Transmit TBI signaling.
125 MHz Reference Clock: May be optionally connected to a 125 MHz
oscillator for 1000 Mb/s mode. If not used should be tied high.
BIOS ROM/Flash Interface
Symbol
MCSN
MD7, MD6,
MD5, MD4/EEDO,
MD3, MD2,
MD1/CFGDISN,
MD0/PMGDISN
MA15/TXD7,
MA14/TXD6,
MA13/TXD5,
MA12/TXD4,
MA11/TXD3,
MA10/TXD2,
MA9/TXD1,
MA8/TXD0,
MA7, MA6,
MA5, MA4/EECLK,
MA3/EEDI, MA2,
MA1, MA0
MWRN
MRDN
Pin No(s)
92
104, 103,
102, 101,
98, 97,
96,
95,
152,
151,
148,
147,
146,
145,
142,
141,
114, 113,
112, 109,
108, 107,
106, 105
94
93
Direction
O
I/O
Description
BIOS PROM/Flash Chip Select: During a BIOS ROM/Flash access, this
signal is used to select the ROM device.
BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these
signals are used to transfer data to or from the ROM/Flash device.
MD5:0 and MD7 pin pads have an internal weak pull up.
MD6 pin pad has an internal weak pull down.
O BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these
signals are used to drive the ROM/Flash address.
O BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this signal is
used to enable data to be written to the Flash device.
O BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this signal is
used to enable data to be read from the Flash device.
Note: DP83821 supports NM27LV010 for the ROM interface device.
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DP83821 pdf, datenblatt
3.0 Functional Description (Continued)
CLK
Figure 3-4 Target Read Operation
FRAMEN
AD[31:0]
C/BEN[3:0]
Addr
Data
IRDYN
TRDYN
DEVSELN
PAR
PERRN
3.3.2 Target Write
A Target Write operation starts with the system generating
FRAMEN, Address, and Command (0011b or 0111b). See
Figure 3-5. If the upper 24 bits on the address bus match
CFGIOA:IOBASE (for I/O reads) or CFGMA:MEMBASE
(for memory reads), the DP83821 will generate DEVSELN
2 clock cycles later.
On the 2nd cycle after the assertion of DEVSELN, the
device will monitor the IRDYN signal. If IRDYN is asserted
at that time, the DP83821 will assert TRDYN. On the next
clock the 32-bit double word will be latched in, and TRDYN
will be forced HIGH for 1 cycle and then tri-stated.
Note: Target write operations must be 32-bits wide.
If FRAMEN is asserted beyond the assertion of IRDYN, the
DP83821 will still latch the first double word as described
above, but will also issue a Disconnect. That is, it will
assert the STOPN signal with TRDYN. STOPN will remain
asserted until FRAMEN is detected as deasserted.
CLK
Figure 3-5 Target Write Operation
FRAMEN
AD[31:0]
C/BEN[3:0]
Addr
Data
IRDYN
TRDYN
DEVSELN
PAR
PERRN
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