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PDF DP83816 Data sheet ( Hoja de datos )
| Número de pieza | DP83816 | |
| Descripción | 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 2005
www.DataSheet4U.com
DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access
Controller and Physical Layer (MacPHYTER-II™)
General Description
DP83816 is a single-chip 10/100 Mb/s Ethernet Controller
for the PCI bus. It is targeted at low-cost, high volume PC
motherboards, adapter cards, and embedded systems.
The DP83816 fully implements the V2.2 33 MHz PCI bus
interface for host communications with power management
support. Packet descriptors and data are transferred via
bus-mastering, reducing the burden on the host CPU. The
DP83816 can support full duplex 10/100 Mb/s transmission
and reception, with minimum interframe gap.
The DP83816 device is an integration of an enhanced
version of the National Semiconductor PCI MAC/BIU
(Media Access Controller/Bus Interface Unit) and a 3.3V
CMOS physical layer interface.
Features
— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports
traditional data rates of 10 Mb/s Ethernet and 100 Mb/s
Fast Ethernet (via internal phy)
— Bus master - burst sizes of up to 128 dwords (512 bytes)
— BIU compliant with PC 97 and PC 98 Hardware Design
Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,
PCI Power Management Specification v1.1, OnNow
Device Class Power Management Reference
Specification - Network Device Class v1.0a
— Wake on LAN (WOL) support compliant with PC98,
PC99, SecureOn, and OnNow, including directed
packets, Magic Packet, VLAN packets, ARP packets,
pattern match packets, and Phy status change
— Clkrun function for PCI Mobile Design Guide
— Virtual LAN (VLAN) and long frame support
— Support for IEEE 802.3x Full duplex flow control
— Extremely flexible Rx packet filtration including: single
address perfect filter with MSb masking, broadcast, 512
entry multicast/unicast hash table, deep packet pattern
matching for up to 4 unique patterns
— Statistics gathered for support of RFC 1213 (MIB II),
RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing
CPU overhead for management
— Internal 2 KB Transmit and 2 KB Receive data FIFOs
— Serial EEPROM port with auto-load of configuration data
from EEPROM at power-on
— Flash/PROM interface for remote boot support
— Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical
layer
— IEEE 802.3 10BASE-T transceiver with integrated filters
— IEEE 802.3u 100BASE-TX transceiver
— Fully integrated ANSI X3.263 compliant TP-PMD
physical sublayer with adaptive equalization and
Baseline Wander compensation
— IEEE 802.3u Auto-Negotiation - advertised features
configurable via EEPROM
— Full Duplex support for 10 and 100 Mb/s data rates
— Single 25 MHz reference clock
— 144-pin LQFP package
— Low power 3.3V CMOS design with typical consumption
of 383 mW operating, 297 mW during WOL and 53 mW
during sleep mode
— IEEE 802.3u MII for connecting alternative external
Physical Layer Devices
— 3.3V signalling with 5V tolerant I/O.
System Diagram
PCI Bus
DP83816
Isolation
10/100 Twisted Pair
BIOS ROM EEPROM
(optional) (optional)
MacPHYTER-II is a trademark of National Semiconductor Corporation.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
© 2005 National Semiconductor Corporation
www.national.com
1 page  
2.0 Pin Description
PCI Bus Interface
Symbol
AD[31-0]
CBEN[3-0]
PCICLK
DEVSELN
FRAMEN
GNTN
IDSEL
INTAN
IRDYN
PAR
PERRN
REQN
RSTN
LQFP Pin
No(s)
Dir
Description
66, 67, 68, 70, I/O Address and Data: Multiplexed address and data bus. As a bus master, the
71, 72, 73, 74,
DP83816 will drive address during the first bus phase. During subsequent phases,
78, 79, 81, 82,
the DP83816 will either read or write data expecting the target to increment its
83, 86, 87, 88,
address pointer. As a bus target, the DP83816 will decode each address on the bus
101, 102, 104,
and respond if it is the target being addressed.
105, 106, 108,
109, 110, 112,
113, 115, 116,
118, 119, 120,
121
75, I/O Bus Command/Byte Enable: During the address phase these signals define the
89, “bus command” or the type of bus transaction that will take place. During the data
100, phase these pins indicate which byte lanes contain valid data. CBEN[0] applies to
111 byte 0 (bits 7-0) and CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian
Mode. In Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and CBEN[0]
applies to byte 3 (bits 7-0).
60 I Clock: This PCI Bus clock provides timing for all bus phases. The rising edge
defines the start of each phase. The clock frequency ranges from 0 to 33 MHz.
95 I/O Device Select: As a bus master, the DP83816 samples this signal to insure that the
destination address for the data transfer is recognized by a PCI target. As a target,
the DP83816 asserts this signal low when it recognizes its address after FRAMEN
is asserted.
91 I/O Frame: As a bus master, this signal is asserted low to indicate the beginning and
duration of a bus transaction. Data transfer takes place when this signal is asserted.
It is de-asserted before the transaction is in its final phase. As a target, the device
monitors this signal before decoding the address to check if the current transaction
is addressed to it.
63 I Grant: This signal is asserted low to indicate to the DP83816 that it has been
granted ownership of the bus by the central arbiter. This input is used when the
DP83816 is acting as a bus master.
76 I Initialization Device Select: This pin is sampled by the DP83816 to identify when
configuration read and write accesses are intended for it.
61 O Interrupt A: This signal is asserted low when an interrupt condition occurs as
defined in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable
registers.
92 I/O Initiator Ready: As a bus master, this signal will be asserted low when the
DP83816 is ready to complete the current data phase transaction. This signal is
used in conjunction with the TRYDN signal. Data transaction takes place at the
rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a target,
this signal indicates that the master has put the data on the bus.
99 I/O Parity: This signal indicates even parity across AD[31-0] and CBEN[3-0] including
the PAR pin. As a master, PAR is asserted during address and write data phases.
As a target, PAR is asserted during read data phases.
97 I/O Parity Error: The DP83816 as a master or target will assert this signal low to
indicate a parity error on any incoming data (except for special cycles). As a bus
master, it will monitor this signal on all write operations (except for special cycles).
64 O Request: The DP83816 will assert this signal low to request ownership of the bus
from the central arbiter.
62 I Reset: When this signal is asserted all PCI bus outputs of DP83816 will be in TRI-
STATE® and the device will be put into a known state.
5 www.national.com
5 Page 
3.0 Functional Description
DP83816 consists of a MAC/BIU (Media Access
Controller/Bus Interface Unit), a physical layer interface,
SRAM, and miscellaneous support logic. The MAC/BIU
includes the PCI bus, BIOS ROM and EEPROM interfaces,
and an 802.3 MAC. The physical layer interface used is a
single-port version of the 3.3V DsPhyterII. Internal memory
consists of one - 0.5 KB and two - 2 KB SRAM blocks.
TPRDP/M
3V DSP Physical Layer
25 MHz Clk
SRAM
RX-2 KB
SRAM
RXFilter
.5 KB
SRAM
TX-2 KB
RAM
BIST
Logic
Interface
Logic
TPTDP/M
MII RX
MII TX
MII Mgt
BIOS ROM Cntl
BIOS ROM Data
EEPROM/LEDs
PCI CLK
PCI CNTL
PCI AD
MAC/BIU
DP83816
Figure 3-1 DP83816 Functional Block Diagram
11 www.national.com
11 Page | ||
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| PDF Descargar | [ Datasheet DP83816.PDF ] | |
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