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PDF ADUC7129 Data sheet ( Hoja de datos )
| Número de pieza | ADUC7129 | |
| Descripción | Precision Analog Microcontroller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADUC7129 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Precision Analog Microcontroller
ARM7TDMI MCU with 12-Bit ADC and DDS DAC
ADuC7128/ADuC7129
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 14 analog-to-digital converter (ADC) channels
Fully differential and single-ended modes
0 to VREF analog input range
10-bit digital-to-analog converter (DAC)
32-bit 21 MHz direct digital synthesis (DDS)
Current-to-voltage (I/V) conversion
Integrated second-order low-pass filter (LPF)
DDS input to DAC
100 Ω line driver
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
External watch crystal/clock source
41.78 MHz PLL with 8-way programmable divider
Optional trimmed on-chip oscillator
Memorywww.DataSheet4U.com
126 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software triggered in-circuit reprogrammability
On-chip peripherals
2× UART, 2× I2C and SPI serial I/O
Up to 40-pin GPIO port
5× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
16-bit PWM generator
Quadrature encoder
Programmable logic array (PLA)
Power
Specified for 3 V operation
Active mode
11 mA (@ 5.22 MHz)
45 mA (@ 41.78 MHz)
Packages and temperature range
64-lead 9 mm × 9 mm LFCSP package, −40°C to 125°C
64-lead LQFP, −40°C to +125°C
80-lead LQFP, −40°C to +125°C
Tools
Low cost QuickStart development system
Full third-party support
FUNCTIONAL BLOCK DIAGRAM
ADC0
CMP0
CMP1
CMPOUT
VREF
RST
XCLKI
XCLKO
XCLK
MUX T/H
12-BIT SAR
ADC 1MSPS
TEMP
SENSOR
+
–
BAND GAP
REFERENCE
DDS
10-BIT
IOUT DAC
I/IV/V
ADuC7129
LPF
POR
OSC/PLL
PSM
ARM7TDMI-BASED MCU
WITH ADDITIONAL PERIPHERALS
5 GEN PURPOSE
TIMERS
2 kBYTES
62 kBYTES 64 kBYTES 8192 BYTES
WAKE-UP/
FLASH/EE FLASH/EE
SRAM
RTC TIMER
(31k ×
(32k ×
(2k ×
INTERRUPT
16 BITS) 16 BITS)
32 BITS)
CONTROLLER
JTAG
PLA
SPI
I2C
UART0
UART1
GPIO
CONTROL
PWM
QUAD
ENCODER
JTAG
P0.0 P0.7 P1.0 P1.7 P2.0 P2.7 P3.0 P3.3
Figure 1.
VDACOUT
LD1TX
LD2TX
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
S1
S2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
ADuC7128/ADuC7129
Parameter
Relative Accuracy
Differential Nonlinearity, +VE
Differential Nonlinearity, −VE
Offset Error
Gain Error
Voltage Output Settling Time
to 0.1%
Line Driver Output
Total Harmonic Distortion
Output Voltage Swing
COMMON MODE
AC Mode
DC Mode
DIFFERENTIAL INPUT IMPEDANCE
Leakage Current LD1TX, LD2TX
Short-Circuit Current
Line Driver Tx Power-Up Time
COMPARATOR
Input Offset Voltage
www.DataSheet4U.com Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis3, 5
Response Time
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage Temperature Coefficient
Accuracy
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
Power Supply Trip Point Accuracy
GLITCH IMMUNITY ON RST PIN3
WATCHDOG TIMER (WDT)
Timeout Period
FLASH/EE MEMORY7, 8
Endurance
Data Retention
DIGITAL INPUTS
Logic 1 Input Current (Leakage
Current)
Logic 0 Input Current (Leakage
Current)
Input Capacitance
Min Typ
±2
0.35
−0.15
Max
−190
+150
5
Unit
LSB
LSB
LSB
mV
mV
μs
−52
±1.768
1.65
1.5
11 13
±50
AGND
2
±15
1
7
1
dB
V rms
V
V
kΩ
7 μA
mA
20 μs
AVDD − 1.2 V
15
mV
μA
pF
mV
μs
780
−1.3
±3
2.79
3.07
±2.5
50
0
10,000
20
±0.2
−40
−80
15
mV
mV/°C
°C
V
V
%
μs
ms
512 sec
Cycles
Years
±1 μA
−65 μA
+125
μA
pF
Rev. 0 | Page 5 of 92
Test Conditions/Comments
As measured into a range of specified loads
(see Figure 2) at LD1TX and LD2TX, unless
otherwise noted
PLM operating at 691.2 kHz
Each output has a common mode of 0.5 V × AVDD
and swings 0.5 V × VREF above and below this;
VREF is the internal 2.5 V reference
Each output has a common mode of 0.5 V × VREF
and swings 0.6 V × VREF above and below this;
VREF is the internal 2.5 V reference
Line driver buffer disabled
Line driver buffer disabled
No protection diodes, max allowable current
Hysteresis can be turned on or off via the
CMPHYST bit in the CMPCON register
Response time can be modified via the CMPRES
bits in the CMPCON register
Two selectable trip points
Of the selected nominal trip point voltage
TJ = 85°C
All digital inputs, including XCLKI and XCLKO
VINH = VDD or VINH = 5 V
VINL = 0 V, except TDI
VINL = 0 V, TDI Only
5 Page 
ADuC7128/ADuC7129
SPI Timing Specifications
Table 5. SPI Master Mode Timing (PHASE Mode = 1)
Parameter Description
tSL SCLOCK low pulse width1
tSH SCLOCK high pulse width1
tDAV Data output valid after SCLOCK edge
tDSU Data input setup time before SCLOCK edge2
tDHD Data input hold time after SCLOCK edge2
tDF Data output fall time
tDR Data output rise time
tSR SCLOCK rise time
tSF SCLOCK fall time
Min
1 × tUCLK
2 × tUCLK
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
5
5
5
5
1 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD.
2 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
Max
2 × tHCLK + 2 × tUCLK
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.DataSheet4U.com
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI
MISO
tSH
tSL
tDAV
tDF
MSB
tSR
tDR
BIT 6 TO BIT 1
MSB IN
tDSU
tDHD
BIT 6 TO BIT 1
Figure 6. SPI Master Mode Timing (PHASE Mode = 1)
tSF
LSB
LSB IN
Rev. 0 | Page 11 of 92
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC7129.PDF ] | |
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