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| Número de pieza | ECLTSSOP20EVB | |
| Descripción | Evaluation Board Manual | |
| Fabricantes | ON Semiconductor | |
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ECLTSSOP20EVB
Evaluation Board Manual
for High Frequency
TSSOP 20
http://onsemi.com
EVALUATION BOARD MANUAL
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the devices in 20-lead TSSOP package. These evaluation
boards are offered as a convenience for the customers
interested in performing their own engineering assessment
on the general performance of the 20-lead TSSOP device
samples. The board provides a high bandwidth 50 W
controlled impedance environment. Figures 1 and 2 show
the top and bottom view of the evaluation board, which can
be configured in several different ways, depending on
device under test (see Table 1. Configuration List).
This evaluation board manual contains:
• Information on 20-lead TSSOP Evaluation Board
•www.DataSheet4U.com Assembly Instructions
• Appropriate Lab Setup
• Bill of Materials
This manual should be used in conjunction with the device
data sheet, which contains full technical details on the device
specifications and operation.
Board Lay-Up
The 20-lead TSSOP evaluation board is implemented in
four layers with split (dual) power supplies (see Figure 3.
Evaluation Board Lay-Up). For standard ECL lab setup and
test, a split (dual) power supply is essential to enable the 50
W internal impedance in the oscilloscope as a termination for
ECL devices. The first layer or primary trace layer is 0.008″
thick Rogers RO4003 material, which is designed to have
equal electrical length on all signal traces from the device
under the test (DUT) to the sense output. The second layer
is the 1.0 oz copper ground. The FR4 dielectric material is
placed between second and third layer and between third and
fourth layer. The third layer is the power plane (VCC & VEE)
and a portion of this layer is a ground plane. The fourth layer
is the secondary trace layer.
Figure 1. Top View of the 20-lead TSSOP Evaluation Board
© Semiconductor Components Industries, LLC, 2003
May, 2003 - Rev. 1
1
Publication Order Number:
ECLTSSOP20EVB/D
1 page  
ECLTSSOP20EVB
Evaluation Board Assembly Instructions
The 20-lead TSSOP evaluation board is designed for
characterizing devices in a 50 W laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via, which has an option of placing a termination
resistor depending on the input/output configuration (see
Table 1, Configuration List). Table 11 contains the Bill of
Materials for this evaluation board.
Solder the Device on the Evaluation Board
The soldering can be accomplished by hand soldering or
soldering re-flow techniques. Make sure pin 1 of the device
is located next to the white dotted mark and all the pins are
aligned to the footprint pads. Solder the 20-lead TSSOP
device to the evaluation board.
Connecting Power and Ground Planes
For standard ECL lab setup and test, a split (dual) power
supply is required enabling the 50 W internal impedance in
the oscilloscope to be used as a termination of the ECL
signals (VTT = VCC – 2.0 V, in split power supply setup, VTT
is the system ground, VCC is 2.0 V, and VEE is –3.0 V or
–1.3 V; see Table 2, Power Supply Levels).
Table 2. Power Supply Levels
Power Supply
5.0 V
VCC
2.0 V
3.3 V
2.0 V
2.5 V
2.0 V
VEE
-3.0 V
-1.3 V
-0.5 V
GND
0.0 V
0.0 V
0.0 V
Connect three banana jack sockets to VCC, VEE, and GND
labeled holes. Wire bond the appropriate device pin pad on
the bottom side of the board to VCC and VEE power stripes.
(Device specific, please see configuration for each desired
device. See Figure 5)
It is recommended to solder 0.01 mF capacitors to C4 and
C5 to reduce the unwanted noise from the power supplies.
C1, C2, and C3 pads are provided for 0.1 mF capacitor to
further diminish the noise from the power supplies. Adding
capacitors can improve edge rates, reduce overshoot and
undershoot.
Termination
All ECL outputs need to be terminated to VTT (VTT = VCC
–2.0 V = GND) via a 50 W resistor. 0402 chip resistor pads
are provided on the bottom side of the evaluation board to
terminate the ECL driver (More information on termination
is provided in AN8020). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads. For ease of assembly,
it is advised to place and solder termination resistors on its
vertical (side) position, instead of its original or flat position.
Installing the SMA Connectors
Each configuration indicates the number of SMA
connectors needed to populate an evaluation board for a
given configuration. Each input and output requires one
SMA connector. Attach all the required SMA connectors
onto the board and solder the connectors to the board on J1
through J20. Please note that alignment of the signal
connector pin of the SMA can influence the lab results. The
reflection and launch of the signals are largely influenced by
imperfect alignment and soldering of the SMA connector.
Validating the Assembled Board
After assembling the evaluation board, it is recommended
to perform continuity checks on all soldered areas before
commencing with the evaluation process. Time Domain
Reflectometry (TDR) is another highly recommended
validation test.
http://onsemi.com
5
5 Page 
SMA
CONNECTORS
J2
J3
J4
J5
J6
J7
J8
J9
ECLTSSOP20EVB
BANANA JACK
PLUG
0603 CHIP
CAPACITOR
0.1 mF
J19
J18
J16
J15
J13
J12
0603 CHIP
CAPACITOR
0.01 mF
WIRE
NORMAL TOP VIEW
EP57
VEE
VCC
PIN 1
0402 CHIP
RESISTOR
50 W
0805 CHIP
CAPACITOR
0.01 mF
EXPANDED BOTTOM VIEW
EP57
Figure 11. Configuration 6
Table 8. Configuration 6 (Device EP57)
Device J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Connector No Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes No Yes Yes No Yes Yes No
Resistor No Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes No
Power
VCC No No No No No No No No VEE VEE No No VCC No No VCC No No VCC
http://onsemi.com
11
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| Páginas | Total 18 Páginas | |
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