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Número de pieza | PI74SSTVF16857A | |
Descripción | 14-Bit Registered Buffer | |
Fabricantes | Pericom Semiconductor | |
Logotipo | ||
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14-Bit Registered Buffer
Product Features
Product Description
• Designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I output specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging Options (Lead-free packages are available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
PericomSemiconductor’sPI74SSTVF16857A seriesoflogiccircuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857A universal bus driver is designed
for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
Logic Block Diagram
CLK
CLK
RESET
38
39
34
D1
VREF
48
35
R
CLK
D
1 Q1
RESET must be supported with LVCMOS levels as VREF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericom’s PI74SSTVF16857A is characterized for operation from
0° to 70°C.
Product Pin Configuration
TO 13 OTHER CHANNELS
www.DataSheet4U.com
Product Pin Description
PinName Description
RESET
Reset (Active Low)
CLK Clock Input
CLK Clock Input
D Data Input
Q Data Output
GND Ground
VDD
VDDQ
VREF
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Truth Table(1)
Inputs
Outputs
RESET CLK CLK
D
Q
L X XX L
H ↑ ↓H H
Η ↑ ↓L
H L or H L or H X
L
Qo(2)
Notes:
1. H = High Signal Level
2.
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH-to-LOW
Output level before the
indicated steady state
input conditions were
established.
X = Irrelevant
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 48-Pin 39
11 A,K 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
1
PS8687
05/27/03
1 page PI74SSTVF16857A
14-Bit Registered Buffer1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
DC Electrical Characteristics for PC3200
(Over the Operating Range, TA = 0°C to +70°C, VDD = 2.6V ±100mV, VDDQ = 2.6V ±100mV)
Parame te rs
Test Conditions
VCC
M in.
Typ.(1) Max. Units
VIK
VOH
VOL
II All Inputs,
Standby (Static)
IDD Operating Static
Dynamic
Operating -
Clock only
IDDD
Dynamic
Operating - per
each data input
Data inputs
CI CK and CK
RESET
II = –18mA
IOH = –100µA
IOH = –8mA
IOL = 100µA
IOH = 8mA
VI = VDD or GND
RESET = GND
VI = VIH (AC) or VI (AC),
RESET = VDD
RESET = VDD
VI = VIH (AC) or VIL(AC),
CK and CK switching
50% duty cycle
IO = 0
RESET = VDD
VI = VIH (AC) or VIL(AC),
CK and CK switching
50% duty cycle. One data
input switching at half clock
frequency, 50% duty cycle
VI = VREF ± 310mV
VICR= 1.25V, VI(PP) = 360mV
VI = VCC or GND
2.5V
2.5V-2.7V VDD –0.2V
2.5V
1.95
2.5V- 2.7V
2.5V
2.7V
2.7V
2.6V
2.5
2.5
2.5
28
9
–1.2
V
0.2
0.35
5
µA
10
25 mA
µA/
clock
MHz
µA/
clock
MHz
Data
3.5
3.5 pF
3.5
Notes:
4. Typical values are at VDD = Nominal VDD, TA = +25°C.
5
PS8687
05/27/03
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet PI74SSTVF16857A.PDF ] |
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PI74SSTVF16857A | 14-Bit Registered Buffer | Pericom Semiconductor |
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