PDF W3EG7264S-D3 Data sheet ( Hoja de datos )

Número de pieza	W3EG7264S-D3
Descripción	512MB - 64Mx72 DDR SDRAM UNBUFFERED
Fabricantes	White Electronic
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No Preview Available ! White Electronic Designs W3EG7264S-JD3-D3 PRELIMINARY* 512MB – 64Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V JEDECwww.DataSheet4U.com standard 184 pin DIMM package • PCB Height: 30.48mm (1.20") Max DESCRIPTION The W3EG7264S is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualiﬁed or characterized and is subject to change without notice. NOTE: Consult Factory for availability of: * Lead-Free Products * Vendor source control options * Industrial Temperature option Clock Speed CL-tRCD-tRP DDR400 @CL=3 200MHz 3-3-3 OPERATING FREQUENCIES DDR333 @CL=2.5 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 May 2005 Rev. 5 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3EG7264S-JD3-D3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V Includes DDR SDRAM component only Parameter Symbol Conditions Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. Precharge Power- IDD2P All device banks idle; Power-down Down Standby Current mode; tCK=tCK (MIN); CKE=(low) Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current IDD3P One device bank active; Power- Down mode; tCK (MIN); CKE=(low) Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. Auto Refresh Current IDD5 tRC = tRC (MIN) Self Refresh Current IDD6 CKE ≤ 0.2V Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR400@ CL=3 Max 1395 1665 45 495 405 540 1710 1758 3105 45 4050 DDR333@ CL=2.5 Max 1170 1440 45 405 315 450 1485 1575 2610 45 3645 DDR266@ CL=2 Max 1170 1440 45 405 315 450 1485 1575 2610 45 3645 DDR266@ CL=2.5 Max 1170 1440 45 405 315 450 1485 1575 2610 45 3645 DDR200@ CL=2 Max Units 1170 mA 1440 mA 45 rnA 405 mA 315 mA 450 mA 1485 mA 1575 rnA 2610 mA 45 mA 3645 mA May 2005 Rev. 5 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs Document Title 512MB – 64Mx72 DDR SDRAM UNBUFFERED Revision History Rev # Rev 0 Rev 1 Rev 2 Rev 3 Rev 4 Rev 5 History Created Datasheet Corrected Mechanical Drawing 2.1 Added document title page 2.2 Removed "ED" for Part Marking 3.1 Added 333 and 400 MHz speed 3.2 Added lead-free and RoHS notes 4.1 Updated AC, IDD & CAP speciﬁcations 4.2 Corrected Mo drawing 4.3 Added lead-free and RoHS note 4.4 Added source control options 4.5 Added industrial temperature option 5.1 Added JEDEC Standard (JD3) Package Option 5.2 D3 Not Recommended For New Designs W3EG7264S-JD3-D3 PRELIMINARY Release Date Status 3-6-02 Advanced 1-30-03 Advanced 4-27-04 Preliminary 12-04 Preliminary 2-05 Preliminary 5-05 Preliminary May 2005 Rev. 5 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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