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W3EG7263S-D3 Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3EG7263S-D3
Beschreibung 512MB- 64Mx72 DDR SDRAM REGISTERED
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 13 Seiten
W3EG7263S-D3 Datasheet, Funktion
White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY*
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL
FEATURES
DESCRIPTION
Double-data-rate architecture
Clock Speeds: 100MHz, 133MHz and 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power supply: VCC: 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
www.DataSheet4U.com Package height options:
JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
The W3EG7263S is a 64Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
component. The module consists of eighteen 64Mx4 DDR
SDRAMs in 66 pin TSOP package mounted on a 184 Pin
FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
April 2004
Rev. # 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3EG7263S-D3 Datasheet, Funktion
White Electronic Designs
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE BANK
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRCD = 2*tCK, tRAg = 5*tCK
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR333 (166MHz, CL = 2.5) : tCK = 6ns, BL = 4,
tRCD = 10*tCK, tRAg = 7*tCK
Read: A0 N N R0 N P0 N N N A0 N — repeat the
same timing with random address changing; 50% of
data changing at every burst
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL
= 2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR333 (166MHz, CL = 2.5) : tCK = 6ns, BL = 4,
tRRD = 3*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend: A = Activate, R = Read, W = Write, P =
Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
April 2004
Rev. # 2
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3EG7263S-D3 pdf, datenblatt
White Electronic Designs
Part Number
W3EG7263S335D3
W3EG7263S262D3
W3EG7263S263D3
W3EG7263S265D3
W3EG7263S202D3
ORDERING INFORMATION FOR D3
Speed
CAS Latency tRCD
166MHz/333Mb/s
2.5
3
133MHz/266Mb/s
2
2
133MHz/266Mb/s
2
3
133MHz/266Mb/s
2.5
3
100MHz/200Mb/s
2
2
W3EG7263S-D3
-JD3
-AJD3
PRELIMINARY
tRP Height*
3 28.58 (1.125")
2 28.58 (1.125")
3 28.58 (1.125")
3 28.58 (1.125")
2 28.58 (1.125")
PACKAGE DIMENSIONS FOR D3
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
NOT6.35
(0.250)
NOT RECOMMENDED FOR NEW DESIGNS
D133.48
(5.255" MAX.)
E131.34
D(5.171")
128.95
N(5.077")
4.06
(0.160 MAX)
ECOMME64.77
R(2.550)
6.35
(0.250)
1.78
(0.070)
1.27
49.53 (0.050 TYP.)
(1.950)
3.99
28.58
(0.157)
(1.125 MAX) (MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* All Dimensions are in millimeters and (inches).
April 2004
Rev. # 2
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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