W3EG7218S-AD4 Datasheet PDF - White Electronic
| Part Number | W3EG7218S-AD4 | |
| Description | 128MB - 16Mx72 DDR SDRAM UNBUFFERED | |
| Manufacturers | White Electronic | |
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There is a preview and W3EG7218S-AD4 download ( pdf file ) link at the bottom of this page. Total 13 Pages | ||
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White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY*
128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLL
FEATURES
Double-data-rate architecture
DDR200 and DDR266
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
JEDEC standard 200 pin SO-DIMM package
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Package height options:
AD4: 35.5mm (1.38") and
BD4: 31.75mm (1.25")
DESCRIPTION
The W3EG7218S is a 16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR
SDRAM component. The module consists of nine
16Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic Designs
W3EG7218S-AD4
-BD4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
(Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V)
DDR266
@CL=2
DDR266
@CL=2.5
Parameter
Operating Current
Operating Current
Symbol Conditions
IDD0 One device bank; Active - Precharge; (MIN); DQ,DM and DQS
inputs changing once per clock cycle; Address and control
inputs changing once every two cycles. tRC=tRC(MIN); tCK=tCK
IDD1 One device bank; Active-Read-Precharge; Burst = 2;
tRC=tRC(MIN);tCK=tCK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
Max
1125
1215
Max
990
1080
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
All device banks idle; Power-down mode; tCK=tCK(MIN);
CKE=(low)
CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high;
Address and other control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS and DM.
One device bank active; Power-down mode; tCK(MIN);
CKE=(low)
CS# = High; CKE = High; One device bank; Active-Precharge;
tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; tCK=tCK(MIN); IOUT = 0mA.
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock
cycle.
tRC=tRC(MIN)
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto precharge with
tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change
only during Active Read or Write commands
27
405
225
450
1260
1260
2385
27
3195
27
405
225
450
1170
1125
1980
27
2970
DDR200
@CL=2
Max
990
1080
27
405
225
450
1170
1125
1980
27
2970
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
November 2004
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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| Information | Total 13 Pages | |
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