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W3EG6466S-AD4 Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3EG6466S-AD4
Beschreibung 512MB - 2x32Mx64 DDR SDRAM UNBUFFERED
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 13 Seiten
W3EG6466S-AD4 Datasheet, Funktion
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY*
512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
DDR200, DDR266 and DDR333
• JEDEC design specifications
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: 2.5V ± 0.20V
JEDECwww.DataSheet4U.com standard 200 pin SO-DIMM package
• Package height options:
AD4: 35.5mm (1.38")
BD4: 31.75mm (1.25")
DESCRIPTION
The W3EG6466S is a 2x32Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of sixteen 32Mx8
components as eight 64Mx8 stacked DDR SDRAMs
in 66 pin TSOP packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3EG6466S-AD4 Datasheet, Funktion
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3EG6466S-AD4 pdf, datenblatt
White Electronic Designs
W3EG6466S-AD4
-BD4
PRELIMINARY
ORDERING INFORMATION FOR BD4
Part Number
Speed
Height*
W3EG6466S335BD4
166MHz/333Mbps, CL=2.5
31.75 (1.25)
W3EG6466S262BD4
133MHz/266Mbps, CL=2
31.75 (1.25)
W3EG6466S265BD4
133MHz/266Mbps, CL=2.5
31.75 (1.25)
W3EG6466S202BD4
100MHz/200Mbps, CL=2
31.75 (1.25)
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR BD4
3.98 ± 0.1
(0.157 ± 0.004)
67.56
(2.666) MAX
2.31
(0.091) REF.
11.40
(0.449)
4.19
(0.165)
1.80
(0.071)
47.40
(1.866)
6.35
(0.250)
MAX.
31.75
(1.25)
20
(0.787)
3.98
(0.157) MIN.
1.0 ± 0.1
(0.039 ± 0.004)
* ALL DIMENSIONS ARE IN MILIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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