Datenblatt-pdf.com


W3EG6432S-JD3 Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3EG6432S-JD3
Beschreibung 32Mx64 DDR SDRAM UNBUFFERED
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 13 Seiten
W3EG6432S-JD3 Datasheet, Funktion
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY*
256MB – 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
www.DataSheet4U.com
• VCC
=
VCCQ
=
+2.6V
±0.1V
(200MHz)
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") max
DESCRIPTION
The W3EG6432S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR400 @CL=3
200MHz
3-3-3
DDR333 @CL=2.5
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
May 2005
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3EG6432S-JD3 Datasheet, Funktion
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1.
2.
3.
4.
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
Typical Case : VCC=2.5V, T=25°C
Worst Case : VCC=2.7V, T=10°C
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
May 2005
Rev. 6
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3EG6432S-JD3 pdf, datenblatt
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY
ORDERING INFORMATION FOR D3
Part Number
W3EG6432S403D3
Speed
200MHz/400Mb/s
CAS Latency tRCD
33
tRP
3
Height*
30.48 (1.20")
Temperature
0°C to 70°C
W3EG6432S335D3
166MHz/333Mb/s
2.5 3 3 30.48 (1.20")
0°C to 70°C
W3EG6432S262D3
133MHz/266Mb/s
2
22
30.48 (1.20")
0°C to 70°C
W3EG6432S263D3
133MHz/266Mb/s
2
33
30.48 (1.20")
0°C to 70°C
W3EG6432S265D3
133MHz/266Mb/s
2.5 3 3 30.48 (1.20")
0°C to 70°C
W3EG6432S202D3
100MHz/200Mb/s
2
22
30.48 (1.20")
0°C to 70°C
NOTE:
1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
2 * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
3 * Consult factory for availability for industrial temperature (-40°C to 85°C) options
3.99
(0.157 (2x))
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
PACKAGE DIMENSIONS FOR D3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
64.77
(2.550)
6.35
(0.250)
1.78
(0.070)
1.27
49.53 (0.050 TYP.)
(1.950)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
2.54
(0.100 MAX)
30.48
(1.20)
MAX
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
May 2005
Rev. 6
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





SeitenGesamt 13 Seiten
PDF Download[ W3EG6432S-JD3 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
W3EG6432S-JD332Mx64 DDR SDRAM UNBUFFEREDWhite Electronic
White Electronic

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche