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W3EG64128S-D3 Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3EG64128S-D3
Beschreibung 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 12 Seiten
W3EG64128S-D3 Datasheet, Funktion
White Electronic Designs
W3EG64128S-D3
-JD3
ADVANCED*
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
Clock speeds of 100MHz, 133MHz, 166MHz and
200MHz
DDR200, DDR266, DDR333 and DDR400
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
www.DataSheet4U.com VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166 MHz)
• VCC = VCCQ = +2.6V ±0.1V (200 MHz)
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") MAX
DESCRIPTION
The W3EG64128S is a 2x64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
component. The module consists of sixteen 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR400 @ CL=3
200MHz
3-3-3
DDR333 @ CL=2.5
166MHz
2.5-3-3
DDR266 @ CL=2
133MHz
2-2-2
DDR266 @ CL=2
133MHz
2-3-3
DDR266 @ CL=2.5
133MHz
2.5-3-3
DDR200 @ CL=2
100MHz
2-2-2
May 2005
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3EG64128S-D3 Datasheet, Funktion
White Electronic Designs
W3EG64128S-D3
-JD3
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
4. Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
• DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
1.
2.
3.
4.
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
Typical Case : VCC=2.5V, T=25°C
Worst Case : VCC=2.7V, T=10°C
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
Timing Patterns :
• DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
repeat the same timing with random address
changing; 100% of data changing at every
burst
• DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
• DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
May 2005
Rev. 5
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3EG64128S-D3 pdf, datenblatt
White Electronic Designs
W3EG64128S-D3
-JD3
ADVANCED
Document Title
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
Rev 0
Rev 1
Rev 2
Rev 3
Rev 4
Rev 5
History
Release Date Status
Created Datasheet
1.1 Removed "ED" from part marking
2.1 Added Clock speed 133 & 200MHz
3.1 Added AC specs
3.2 Changed to Advanced until DDR400 is tested
9-18-02
4-04
9-04
11-1-04
Advanced
Primary
Advanced
Advanced
4.1 Added lead-free and RoHS notes
4.2 Added source control notes
4.3 Added industrial temperature option
5-05
Advanced
5.1 Added JEDEC standard PCB
5-05
5.2 D3 option "NOT RECOMMENDED FOR NEW DESIGNS"
Advanced
May 2005
Rev. 5
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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