Datenblatt-pdf.com


W3EG264M72AFSRXXXD3 Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3EG264M72AFSRXXXD3
Beschreibung 1GB - 2x64Mx72 DDR SDRAM REGISTERED ECC
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 13 Seiten
W3EG264M72AFSRXXXD3 Datasheet, Funktion
White Electronic Designs W3EG264M72AFSRxxxD3
ADVANCED*
1GB – 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL, FBGA
FEATURES
Double-data-rate architecture
DDR200, DDR266 and DDR333:
• JEDEC design specifications
Phase-lock loop (PLL) clock driver to reduce
loading
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Dual Rank
Powerwww.DataSheet4U.com supply: VCC 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
• Package height option:
Low-profile: 30.48mm (1.20")
• Consult factory for availability of lead-free
products.
DESCRIPTION
The W3EG264M72AFSR is a 2x64Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of thirtysix 64Mx4, in
FBGA packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
DDR333 @CL=2.5
166MHz
2.5-3-3
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2
133MHz
2-3-3
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
2-2-2
November 2004
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3EG264M72AFSRXXXD3 Datasheet, Funktion
White Electronic Designs W3EG264M72AFSRxxxD3
ADVANCED
Parameter
Operating Current
Operating Current
Precharge Power-
Down Standby Current
Idle Standby Current
Active Power-Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes PLL and register power
Rank 1
Symbol Conditions
IDD0 One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
IDD1 One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
IDD2P All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
IDD2F CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
IDD3P One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
IDD3N CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
IDD4R Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
IDD4W Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
IDD5 tRC = tRC (MIN)
IDD6 CKE 0.2V
IDD7A Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
DDR333@CL=2.5
Max
4995
5805
144
2110
1080
2470
5895
5625
7370
419
10125
DDR266:@CL=2, 2.5
Max
4635
5265
144
1930
900
2110
5085
4815
6650
419
8685
DDR200@CL=2
Max
4635
5265
144
1930
900
2110
5085
4815
6650
419
8685
Units
mA
Rank 2
Standby
State
IDD3N
mA IDD3N
rnA IDD2P
mA IDD2F
mA IDD3P
mA IDD3N
mA IDD3N
rnA IDD3N
mA IDD3N
mA IDD6
mA IDD3N
November 2004
Rev. 1
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3EG264M72AFSRXXXD3 pdf, datenblatt
White Electronic Designs W3EG264M72AFSRxxxD3
ADVANCED
PART NUMBERING GUIDE
WEDC
MEMORY
DDR
GOLD
RANKS
DEPTH (Dual Rank)
BUS WIDTH
x4
FBGA
2.5V
REGISTERED
SPEED (MHz)
PACKAGE
COMPONENT VENDOR
RoHS COMPLIANT
W 3 E G 2 64M 72 A F S R xxx D3 x G
November 2004
Rev. 1
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





SeitenGesamt 13 Seiten
PDF Download[ W3EG264M72AFSRXXXD3 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
W3EG264M72AFSRXXXD31GB - 2x64Mx72 DDR SDRAM REGISTERED ECCWhite Electronic
White Electronic

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche