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W3EG264M64EFSU-D4 Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3EG264M64EFSU-D4
Beschreibung 1GB - 2x64Mx64 DDR SDRAM
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 11 Seiten
W3EG264M64EFSU-D4 Datasheet, Funktion
White Electronic Designs W3EG264M64EFSU-D4
ADVANCED*
1GB – 2x64Mx64 DDR SDRAM, UNBUFFERED, FBGA
FEATURES
Fast data transfer rate: PC-2100, PC-2700 and
PC3200
Clock speeds of 133 MHz, 166 MHz and 200MHz
Supports ECC error detection and correction
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 3 and 4 (clock)
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect (SPD) with EEPROM
VCC = VCCQ = +2.6V ±0.1V (200MHz)
VCC = VCCQ = +2.5V ±0.2V (133 and 166MHz)
www.DataSheet4U.com
Gold edge contacts
Dual Rank
JEDEC standard 200 pin, small-outline, SO-DIMM
package
• PCB height option:
D4: 31.75 mm (1.25”)
DESCRIPTION
The W3EG264M64EFSU is a 2x64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of sixteen 64Mx8 DDR
SDRAMs in FBGA packages mounted on a 200 pin FR4
substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
OPERATING FREQUENCIES
DDR400@CL=3
200MHz
3-3-3
DDR333@CL=2.5
166MHz
2.5-3-3
DDR266@CL=2
133MHz
2-2-2
DDR266@CL=2.5
133MHz
2.5-3-3
August 2005
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3EG264M64EFSU-D4 Datasheet, Funktion
White Electronic Designs W3EG264M64EFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = VCCQ = +2.5V ±0.2V
AC CHARACTERISTICS
403 335 262 265
PARAMETER
SYMBOL
Access window of DQs from CK/CK#
tAC
CK high-level width
tCH
CK low-level width
tCL
Clock cycle time
CL = 3 tCK (3)
CL = 2.5 tCK (2.5)
CL = 2 tCK (2)
DQ and DM input hold time relative to DQS
tDH
DQ and DM input setup time relative to DQS
tDS
DQ and DM input pulse width (for each input)
tDIPW
Access window of DQS from CK/CK#
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
Write command to first DQS latching transition
tDQSS
DQS falling edge to CK rising - setup time
tDSS
DQS falling edge from CK rising - hold time
tDSH
Half clock period
tHP
Data-out high-impedance window from CK/CK#
tHZ
Data-out low-impedance window from CK/CK#
tLZ
Address and control input hold time (fast slew rate)
tIHF
Address and control input setup time (fast slew rate)
tISF
Address and control input hold time (slow slew rate)
tIHS
MIN MAX
-0.65 +0.65
0.45 0.55
0.45 0.55
5 10
0.40
0.40
1.75
-0.55 +0.55
0.35
0.35
0.4
0.72 1.25
0.20
0.20
tCH,tCL
+0.65
-0.65 +0.65
0.60
0.60
0.8
MIN MAX
-0.70 +0.70
0.45 0.55
0.45 0.55
6 13
7.5 13
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.4
0.75 1.25
0.20
0.20
tCH,tCL
+0.70
-0.70
0.75
0.75
0.8
MIN MAX MIN MAX UNITS NOTES
-0.75 +0.75 -0.75 0.75 ns
0.45 0.55 0.45 0.55 tCK 26
0.45 0.55 0.45 0.55 tCK 26
ns 39, 44
7.5 13 7.5 13 ns 39, 44
7.5 13 7.5/10 13 ns 39, 44
0.5 0.5 ns 23, 27
0.5 0.5 ns 23, 27
1.75 1.75
ns 27
-0.75 +0.75 -0.75 +0.75 ns
0.35 0.35
tCK
0.35 0.35
tCK
0.5 0.5 ns 22, 23
0.75 1.25 0.75 1.25 tCK
0.20 0.2
tCK
0.20 0.2
tCK
tCH,tCL
tCH, tCL
ns 30
+0.75
+0.75 ns 16, 36
-0.75 -0.75
ns 16, 36
0.90 0.90
ns 12
0.90 0.90
ns 12
1 1 ns 12
August 2005
Rev. 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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