PDF W3E64M72S-XBX Data sheet ( Hoja de datos )

Número de pieza	W3E64M72S-XBX
Descripción	64Mx72 DDR SDRAM
Fabricantes	White Electronic
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White Electronic Designs W3E64M72S-XBX ADVANCED* 64Mx72 DDR SDRAM FEATURES Data rate = 200, 250, 266 and 333Mbs Package: • 219 Plastic Ball Grid Array (PBGA), 25 x 32mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; center- aligned with data for WRITEs DLLwww.DataSheet4U.com to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRanges Organized as 64M x 72 Weight: W3E64M72S-XBX - 4.5 grams typical * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. BENEFITS 66% Space Savings vs. TSOP Reduced part count 55% I/O reduction vs TSOP Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match GENERAL DESCRIPTION The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 9 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 512MB DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 512MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver.strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte. The 512MB DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. June 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs W3E64M72S-XBX ADVANCED INITIALIZATION DDR SDRAMs must be powered up and initialized in a predeﬁned manner. Operational procedures other than those speciﬁed may result in undeﬁned operation. Power must ﬁrst be applied to VCC and VCCQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VCCQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VCCQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VCC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power- up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisﬁed, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisﬁed.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation. REGISTER DEFINITION MODE REGISTER The Mode Register is used to deﬁne the speciﬁc mode of operation of the DDR SDRAM. This deﬁnition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 3. The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. (Except for bit A8 which is self clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The Mode Register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the speciﬁed time before initiating the subsequent operation. Violating either of these requirements will result in unspeciﬁed operation. Mode register bits A0-A2 specify the burst length, A3 speciﬁes the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode. BURST LENGTH Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 3. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two; by A2-Ai when the burst length is set to four (where Ai is the most signiﬁcant column address for a given conﬁguration); and by A3-Ai when the burst length is set to eight. The remaining (least signiﬁcant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. June 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page White Electronic Designs W3E64M72S-XBX ADVANCED ABSOLUTE MAXIMUM RATINGS Parameter Voltage on VCC, VCCQ Supply relative to Vss Voltage on I/O pins relative to Vss Operating Temperature TA (Mil) Operating Temperature TA (Ind) Operating Temperature TA (Com) Storage Temperature, Plastic Maximum Junction Temperature -1 to 3.6 -0.5V to VCCQ +0.5V -55 to +125 -40 to +85 -0 to +70 -55 to +125 125 Unit V V °C °C °C °C °C NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Input Capacitance: CK/CK# Addresses, BA0-1 Input Capacitance Input Capacitance: All other input-only pins Input/Output Capacitance: I/Os CAPACITANCE (NOTE 13) Symbol CI1 CA CI2 CIO Max TBD TBD TBD TBD Unit pF pF pF pF BGA THERMAL RESISTANCE Description Junction to Ambient (No Airﬂow) Junction to Ball Junction to Case (Top) Symbol Theta JA Theta JB Theta JC Max TBD TBD TBD Units °C/W °C/W °C/W Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.wedc.com in the application notes section for modeling conditions. Notes 1 1 1 White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. June 2005 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 11 Page

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