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W3E32M72SR-XSBX Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3E32M72SR-XSBX
Beschreibung 32Mx72 REGISTERED DDR SDRAM
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 19 Seiten
W3E32M72SR-XSBX Datasheet, Funktion
White Electronic Designs W3E32M72SR-XSBX
32Mx72 REGISTERED DDR SDRAM
FEATURES
„ Registered for enhanced performance of bus
speeds of 200, 250, 266Mb/s
„ Package:
• 208 Plastic Ball Grid Array (PBGA), 16 x 25mm
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CK and CK#)
„ Commands entered on each positive CK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
„ DQSwww.DataSheet4U.com edge-aligned with data for READs; center-
aligned with data for WRITEs
„ DLL to align DQ and DQS transitions with CK
„ Four internal banks for concurrent operation
„ Data mask (DM) pins for masking write data
(one per byte)
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Commercial, Industrial and Military Temperature
Ranges
„ Organized as 32M x 72
„ Weight: W3E32M72SR-XSBX - 2.5 grams typical
* This product is subject to change or cancellation without notice.
BENEFITS
„ 74% SPACE SAVINGS vs. TSOP
„ Reduced part count
„ 51% I/O reduction vs TSOP
„ Glueless connection to PCI bridge/memory
controller
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at the
receiver.strobe transmitted by the DDR SDRAM during
READs and by the memory contoller during WRITEs. DQS
is edge-aligned with data for READs and center-aligned
with data for WRITEs. Each chip has two data strobes, one
for the lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3E32M72SR-XSBX Datasheet, Funktion
White Electronic Designs W3E32M72SR-XSBX
device loses power. The enabling of the DLL should always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
SPEED
-200
-250
-266
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
75
100
100
CAS
LATENCY = 2.5
100
125
133
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specied time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecied operation.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specied to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM.
The SDRAM is effectively deselected. Operations already
in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses.
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 3
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3E32M72SR-XSBX pdf, datenblatt
White Electronic Designs W3E32M72SR-XSBX
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46, 54)
VCC, VCCQ = +2.5V ± 0.2V; -55°C TA +125°C
MAX
Parameter/Condition
Symbol 250MHz 200MHz
266MHz
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 47)
ICC0 650 575
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =
0mA; Address and control inputs changing once per clock cycle (22, 47)
ICC1 800 725
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = ICC2P 25
LOW; (23, 32, 49)
25
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (50)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE =
LOW (23, 32, 49)
ICC2F 225 200
ICC3P 175 150
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK ICC3N 250 225
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once
per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 47)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
AUTO REFRESH CURRENT
tREFC = tRC (MIN) (49)
tREFC = 7.8125µs (27, 49)
SELF REFRESH CURRENT: CKE 0.2V
Standard (11)
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ or WRITE commands. (22, 48)
ICC4R
ICC4W
ICC5
ICC5A
ICC6
ICC7
825
755
1,450
50
25
2,000
725
675
1,400
50
25
1,750
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
White Electronic Designs Corp. reserves the right to change products or specications without notice.
July 2006
Rev. 3
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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