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PDF W3E32M64S-XSBX Data sheet ( Hoja de datos )
| Número de pieza | W3E32M64S-XSBX | |
| Descripción | 32Mx64 DDR SDRAM | |
| Fabricantes | White Electronic | |
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White Electronic Designs
W3E32M64S-XSBX
32Mx64 DDR SDRAM
FEATURES
DDR SDRAM rate = 200, 250, 266, 333**
Package:
• 208 Plastic Ball Grid Array (PBGA),
13 x 22mm
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs (CK and CK#)
Commands entered on each positive CK
edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQSwww.DataSheet4U.com edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military
TemperatureRanges
Organized as 32M x 64
• Can be user organized as 2x32Mx32 or
4x32Mx16
Weight: W3E32M64S-XSBX — 1.5 grams typical
* This product is subject to change without notice.
** For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature
CL = 3.
BENEFITS
73% Space Savings vs. FPBGA
• 43% Space Savings vs TSOP
Reduced part count
21% I/O reduction vs TSOP
• 13% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Upgradeable to 64M x 64 density (contact factory
for information)
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
July 2006
Rev. 5
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3E32M64S-XSBX
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLL should always
July 2006
Rev. 5
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
W3E32M64S-XSBX
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ 125°C
Symbol
Min
VIH VREF + 0.5
VIL -
Max
-
VREF - 0.5
Units
V
V
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46)
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 47)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT =
0mA; Address and control inputs changing once per clock cycle (22, 47)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE
= LOW; (23, 32, 49)
MAX
Symbol
333Mbs
250Mbs
266Mbs
200Mbs
Units
ICC0 520 520 460 mA
ICC1 640 640 580 mA
ICC2P
20
20
20 mA
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (50)
ICC2F
180
180
160
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE =
LOW (23, 32, 49)
ICC3P
140
140
120
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK =
tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing ICC3N 200 200 180
once per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 47)
ICC4R
660
660
580
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
ICC4W 780 640 540
AUTO REFRESH CURRENT
tREFC = tRFC (MIN) (49)
tREFC = 7.8125µs (27, 49)
ICC5
ICC5A
1,160
40
1,160
40
1,120
40
SELF REFRESH CURRENT: CKE 0.2V
Standard (11)
ICC6 20 20 20
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ or WRITE commands. (22, 48)
ICC7
1,620
1,600 1,400
mA
mA
mA
mA
mA
mA
mA
mA
mA
July 2006
Rev. 5
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet W3E32M64S-XSBX.PDF ] | |
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