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W3E32M64S-XBX Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3E32M64S-XBX
Beschreibung 32Mx64 DDR SDRAM
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 17 Seiten
W3E32M64S-XBX Datasheet, Funktion
White Electronic Designs
W3E32M64S-XBX
www.DataSheet4U.com
32Mx64 DDR SDRAM
FEATURES
„ DDR SDRAM rate = 200, 250, 266, 333Mb/s
„ Package:
• 219 Plastic Ball Grid Array (PBGA),
25mm x 25mm, 625mm2
„ 2.5V ±0.2V core power supply
„ 2.5V I/O (SSTL_2 compatible)
„ Differential clock inputs (CK and CK#)
„ Commands entered on each positive CK edge
„ Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
„ Programmable Burst length: 2,4 or 8
„ Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
„ DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
„ DLL to align DQ and DQS transitions with CLK
„ Four internal banks for concurrent operation
„ Data mask (DM) pins for masking write data
(one per byte)
„ Programmable IOL/IOH option
„ Auto precharge option
„ Auto Refresh and Self Refresh Modes
„ Commercial, Industrial and Military
TemperatureRanges
„ Organized as 32M x 64
„ User congurable as 2x32Mx32 or 4x32Mx16
„ Pinout compatible with previous W3E16M64S-XBX
version.
„ Weight: W3E32M64S-XBX - 2.5 grams typical
BENEFITS
„ 41% SPACE SAVINGS vs. TSOP
„ Reduced part count
„ Reduced trace lengths for lower parasitic
capacitance
„ Suitable for hi-reliability applications
„ Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 256MByte (2Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
The 256MB DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 256MB DDR SDRAM effectively consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
The 256MB DDR SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
* This product subject to change without notice.
July 2006
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3E32M64S-XBX Datasheet, Funktion
White Electronic Designs
W3E32M64S-XBX
and QFC. These functions are controlled via the bits shown
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLL should always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
Data Rate
CAS LATENCY = 2 CAS LATENCY = 2.5
-200 75 100
-250
100
125
-266
100
133
-333 - 166
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specied time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecied operation.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specied to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-12 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-9 selects
the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses.
July 2006
Rev. 3
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3E32M64S-XBX pdf, datenblatt
White Electronic Designs
W3E32M64S-XBX
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 1-5, 14-17, 33)
Parameter
Access window of DQs from CLK/CLK#
CLK high-level width (30)
CLK low-level width (30)
Clock cycle time
CL = 2.5 (45, 52)
CL = 2 (45, 52)
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to rst DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
Data-out high-impedance window from CLK/CLK# (18, 42)
Data-out low-impedance window from CLK/CLK# (18, 43)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to rst DQ to go non-valid, per access (25, 26)
Data hold skew factor
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble (42)
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time (20, 21)
DQS write postamble (19)
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
REFRESH to REFRESH command interval (23)
Average periodic refresh interval (23)
Terminating voltage delay to VCC (53)
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
Symbol
tAC
tCH
tCL
tCK (2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tMRD
tQH
tQHS
tRAS
tRAP
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
na
tREFC
tREFI
tVTD
tXSNR
tXSRD
333 Mbs CL 2.5
-0.70 +0.70
0.45 0.55
0.45 0.55
7.5 13
10 13
0.45
0.45
1.75
-0.60 +0.60
0.35
0.35
0.45
0.75 1.25
0.2
0.2
tCH, tCL
+0.70
-0.7
0.75
0.75
0.8
0.8
12
tHP - tQHS
0.55
42 70,000
15
60
72
15
15
0.9 1.1
0.4 0.6
12
0.25
0
0.4 0.6
15
1
tQH - tDQSQ
70.3
7.8
0
75
200
266 Mbs CL 2.5
200 CL 2
Min Max
-0.75 +0.75
0.45 0.55
0.45 0.55
7.5 13
10 13
0.5
0.5
1.75
-0.75 +0.75
0.35
0.35
0.5
0.75 1.25
0.2
0.2
tCH, tCL
+0.75
-0.75
0.90
0.90
1
1
15
tHP - tQHS
0.75
40 120,000
20
65
75
20
20
0.9 1.1
0.4 0.6
15
0.25
0
0.4 0.6
15
1
tQH - tDQSQ
70.3
7.8
0
75
200
250 Mbs CL2.5
200 Mbs CL2
Min Max
-0.8 +0.8
0.45 0.55
0.45 0.55
8 13
10 13
0.6
0.6
2
-0.8 +0.8
0.35
0.35
0.6
0.75 1.25
0.2
0.2
tCH, tCL
+0.8
-0.8
1.1
1.1
1.1
1.1
16
tHP - tQHS
1
40 120,000
20
70
80
20
20
0.9 1.1
0.4 0.6
15
0.25
0
0.4 0.6
15
1
tQH - tDQSQ
70.3
7.8
0
80
200
200 Mbs CL2.5
150 Mbs CL2
Min Max
-0.8 +0.8
0.45 0.55
0.45 0.55
10 13
13 15
0.6
0.6
2
-0.8 +0.8
0.35
0.35
0.6
0.75 1.25
0.2
0.2
tCH, tCL
+0.8
-0.8
1.1
1.1
1.1
1.1
16
tHP - tQHS
1
40 120,000
20
70
80
20
20
0.9 1.1
0.4 0.6
15
0.25
0
0.4 0.6
15
1
tQH - tDQSQ
70.3
7.8
0
80
200
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
ns
ns
tCK
July 2006
Rev. 3
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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