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W3E232M16S-XSTX Schematic ( PDF Datasheet ) - White Electronic

Teilenummer W3E232M16S-XSTX
Beschreibung 2x32Mx16bit DDR SDRAM
Hersteller White Electronic
Logo White Electronic Logo 




Gesamt 22 Seiten
W3E232M16S-XSTX Datasheet, Funktion
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
www.DataSheet4U.com
2x32Mx16bit DDR SDRAM
FEATURES
Double-data-rate architecture; two data transfers
per clock cycle
Data rate = 200, 266, 333, 400 Mbs
Package:
• 66pin TSOP II package
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Differential clock inputs(CK and CK#)
DLL aligns DQ and DQS transition with CK
MRS cycle with address key programs
• Read latency : 2, 2.5 , 3 (Clock)
• Burst length (2, 4, or 8)
• Burst type (sequential & interleave)
Auto & Self refresh Modes
RoHS Compliant
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
Four internal banks for concurrent operation
Data mask (DM) pins for masking write data
(one per byte)
Programmable IOL/IOH option
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, and Industrial Temperature Ranges
Organized as 2X32M x 16
* This product is under development, is not qualified +and is subject to change
without notice.
Speed @CL2
Speed @CL2.5
Speed @CL3
* CL = CAS Latency
DDR400
166MHz
200MHz
OPERATING FREQUENCIES
DDR333
133MHz
166MHz
DDR266
133MHz
133MHz
FUNCTIONAL BLOCK DIAGRAM
CK, CK#, CAS, LDM, UDM
RAS#, WE#, UDQS, LDQS
CS0#, CKE0
32Mx16
CS1#, CKE1
32Mx16
A0-A12, BA0, BA1
I/O0 ~ I/O15
DDR200
100MHz
133MHz
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






W3E232M16S-XSTX Datasheet, Funktion
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
SPEED
-200
-266
-333
-400
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
75
100
-
CAS
LATENCY = 2.5
100
133
166
≤ 166
CAS
LATENCY = 3
-
-
166
200
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLL should always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating
any subsequent operation. Violating either of these
requirements could result in unspecified operation.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during power-
up initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.device loses power. The enabling
of the DLL should always be followed by a LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL.The extended mode register
must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified
time before initiating any subsequent operation. Violating
either of these requirements could result in unspecified
operation.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









W3E232M16S-XSTX pdf, datenblatt
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V ± 0.2V; -55°C TA +125°C
Symbol
VIH
VIL
Min
VREF +0.310
Max
VREF -0.310
Units
V
V
IDD SPECIFICATIONS AND CONDITIONS
-40°C ≤ TA +85°C; VccQ = +2.6 ±0.1V, Vcc = +2.6V ±0.1V Notes: 1-5, 10, 12, 14, 46
Parameter/Condition
Symbol
Max
DDR400
OPERATING CURRENT: One bank; Active-Precharge;
IDD0 310
tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs changing
once per clock cycle
IDD1
370
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode;
tCK=tCK (MIN); CKE = (LOW)
IDD2P
10
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN
= VREF for DQ, DQS, and DM
IDD2F
110
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK=tCK (MIN); CKE = (LOW)
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN);
IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN);
IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN)
DQ, DM, and DQS inputs changing twice per clock cycle
IDD3P
IDD3N
IDD4R
IDD4W
90
120
380
380
AUTO REFRESH BURST CURRENT:
tREFC = tRFC(MIN)
tREFC = 7.8us
SELF REFRESH CURRENT; CKE ≤0.2V
Standard
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed:
tCK=tCK (MIN); Address and control inputs change only during Active READ, or WRITE
commands
IDD5
IDD5A
IDD6
IDD7
690
22
10
900
Units
mA
Notes
22, 47
mA 22, 47
mA 23, 32, 49
mA 50
mA 23, 32, 49
mA 22
mA 22, 47
mA 22
mA 49
mA 27, 47
mA 11
mA 22, 48
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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