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PDF ADC14C080 Data sheet ( Hoja de datos )
| Número de pieza | ADC14C080 | |
| Descripción | (ADC14Cxxx) A/D Converter | |
| Fabricantes | National Semiconductor | |
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ADVANCE INFORMATION
September 2006
www.DataSheet4U.com
ADC14C065/ADC14C080/ADC14C095/ADC14C105
14-Bit, 65/80/95/105 MSPS A/D Converter
General Description
NOTE: This is Advance Information for products cur-
rently in development. ALL specifications are design
targets and are subject to change.
The ADC14C065, ADC14C080, ADC14C095, and
ADC14105 are high-performance CMOS analog-to-digital
converters capable of converting analog input signals into
14-bit digital words at rates up to 65/80/95/105 Mega
Samples Per Second (MSPS) respectively. These convert-
ers use a differential, pipelined architecture with digital error
correction and an on-chip sample-and-hold circuit to mini-
mize power consumption and the external component count,
while providing excellent dynamic performance. A unique
sample-and-hold stage yields a full-power bandwidth of 1
GHz. The ADC14C065/080/095/105 may be operated from a
single +3.3V power supply and consumes low power.
A separate +2.5V supply may be used for the digital output
interface which allows lower power operation with reduced
noise. A power-down feature reduces the power consump-
tion to very low levels while still allowing fast wake-up time to
full operation. The differential inputs provide a 2V full scale
differential input swing. A stable 1.2V internal voltage refer-
ence is provided, or the ADC14C065/080/095/105 can be
operated with an external 1.2V reference. Output data for-
mat (offset binary versus 2’s complement) and duty cycle
stabilizer are pin-selectable. The duty cycle stabilizer main-
tains performance over a wide range of clock duty cycles.
The ADC14C065/080/095/105 is available in a 32-lead LLP
package and operates over the industrial temperature range
of −40˚C to +85˚C.
Features
n 1 GHz Full Power Bandwidth
n Internal sample-and-hold circuit
n Low power consumption
n Internal precision reference
n Data Ready output clock
n Clock Duty Cycle Stabilizer
n Single +3.3V supply operation
n Power-down mode
n Offset binary or 2’s complement output data format
n 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)
Key Specifications
n For ADC14C105
n Resolution
n Conversion Rate
n SNR (fIN = 240 MHz)
n SFDR (fIN = 240 MHz)
n Full Power Bandwidth
n Power Consumption
14 Bits
105 MSPS
72 dBFS (typ)
83 dBFS (typ)
1 GHz (typ)
400 mW (typ)
Applications
n High IF Sampling Receivers
n Wireless Base Station Receivers
n Test and Measurement Equipment
n Communications Instrumentation
n Portable Instrumentation
Connection Diagram
© 2006 National Semiconductor Corporation DS202098
20209801
www.national.com
1 page  
Absolute Maximum Ratings (Notes 1,
3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VA, VDR)
Voltage on Any Pin
(Not to exceed 4.2V)
−0.3V to 4.2V
−0.3V to (VA +0.3V)
Input Current at Any Pin other
±5 mA
than Supply Pins (Note 4)
Package Input Current (Note
±50 mA
4)
Max Junction Temp (TJ)
Thermal Resistance (θJA)
ESD Rating
+150˚C
30˚C/W
Human Body Model (Note 6)
2500V
Machine Model (Note 6)
250V
Storage Temperature
−65˚C to +150˚C
Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 7)
Operating Ratings (Notes 1, 3)
Operating Temperature
Supply Voltage (VA)
(ADC14C065,ADC14C080)
(ADC14C095,ADC14C105)
Output Driver Supply (VDR)
Clock Duty Cycle
(DCS Enabled)
(DCS disabled)
VCM
|AGND-DRGND|
−40˚C ≤ TA ≤ +85˚C
+2.7V to +3.6V
+3.0V to +3.6V
+2.25V to VA
30/70 %
45/55 %
1.4V to 1.6V
≤100mV
ADC14C065 Converter Electrical Characteristics
This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifica-
tions cannot be guaranteed until device characterization has taken place.
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 65 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
Limits
(Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
14 Bits (min)
INL Integral Non Linearity (Note 11)
±1.5
LSB (max)
LSB (min)
DNL
Differential Non Linearity
±0.5
LSB (max)
LSB (min)
Under Range Output Code
00
Over Range Output Code
16383 16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCMO
Common Mode Output Voltage
1.45
1.5
1.55
V (min)
V (max)
Analog Input Common Mode
VCM
Voltage
1.4
1.5
1.6
V (min)
V (max)
CIN
VIN Input Capacitance (each pin to
GND) (Note 12)
VIN = 1.5 Vdc
± 0.5 V
(CLK LOW)
(CLK HIGH)
8.5
3.5
pF
pF
VREF
External Reference Voltage
1.20
1.176
1.224
V (min)
V (max)
5 www.national.com
5 Page 
ADC14C095 Dynamic Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA
≤ TMAX. All other limits apply for TA = 25˚C (Note 8) (Note 9)
Symbol
Parameter
Conditions
Typical
Limits
(Note 10)
Units
(Limits)
SINAD
Signal-to-Noise and Distortion
Ratio
fIN = 10 MHz
fIN = 70 MHz
fIN = 240 MHz
73.5
71.7
71.6
dBFS
dBFS
dBFS
ADC14C095 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Boldface limits apply for TMIN ≤ TA ≤
TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symbol
Parameter
Conditions
Typical
Limits
(Note 10)
Units
(Limits)
DIGITAL INPUT CHARACTERISTICS (CLK, PD)
VIN(1)
Logical “1” Input Voltage
VD = 3.6V
VIN(0)
Logical “0” Input Voltage
VD = 3.0V
IIN(1)
Logical “1” Input Current
VIN = 3.3V
IIN(0)
Logical “0” Input Current
VIN = 0V
CIN Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)
2.0 V (min)
0.8 V (max)
10 µA
−10 µA
5 pF
VOUT(1)
VOUT(0)
+ISC
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Short Circuit Source
Current
IOUT = −0.5 mA , VDR = 1.8V
IOUT = 1.6 mA, VDR = 1.8V
VOUT = 0V
1.2 V (min)
0.4 V (max)
−10 mA
−ISC
Output Short Circuit Sink Current
COUT
Digital Output Capacitance
POWER SUPPLY CHARACTERISTICS
VOUT = VDR
10 mA
5 pF
IA Analog Supply Current
Full Operation
IDR Digital Output Supply Current
Full Operation (Note 13)
Power Consumption
Excludes IDR (Note 13)
Power Down Power Consumption Clock disabled
115
14.5
380
5
mA (max)
mA
mW (max)
mW
ADC14C095 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF
= +1.2V, fCLK = 95 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25˚C. Timing measurements are taken at
50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25˚C (Notes 8, 9)
Symb
Parameter
Conditions
Typical
(Note 10)
Limits
Units
(Limits)
Maximum Clock Frequency
95 MHz (max)
Minimum Clock Frequency
20 MHz (min)
tCH
tCL
tCONV
Clock High Time
Clock Low Time
Conversion Latency
5 ns
5 ns
Clock
7
Cycles
tOD Output Delay of CLK to DATA
Relative to rising edge of CLK
2 ns (min)
4
6 ns (max)
tSU Data Output Setup Time
tH Data Output Hold Time
tAD Aperture Delay
tAJ Aperture Jitter
Relative to DRDY
Relative to DRDY
4 ns (min)
4 ns (min)
0.6 ns
0.1 ps rms
11 www.national.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADC14C080.PDF ] | |
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