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PDF ADC083000 Data sheet ( Hoja de datos )
| Número de pieza | ADC083000 | |
| Descripción | Low Power A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
March 2007
ADC083000
8-Bit, 3 GSPS, High Performance, Low Power A/D
Converter
General Description
Note: This product is currently in development. - ALL
specifications are design targets and are subject to
change.
The ADC083000 is a single, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 3.4 GSPS. Consuming
a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters up to Nyquist, producing
a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz
input signal and a 3 GHz sample rate while providing a 10-18
Bit Error Rate, (BER). The ADC083000 achieves a 3 GSPS
sampling rate by utilizing both the rising and falling edge of a
1.5 GHz input clock. Output formatting is offset binary and the
LVDS digital outputs are compliant with IEEE 1596.3-1996,
with the exception of an adjustable common mode voltage
between 0.8V and 1.2V.
www.DataSheet4U.com The ADC has a 1:4 demultiplexer that feeds four LVDS buses
and reduces the output data rate on each bus to a quarter of
the sampling rate. The ADC can be programmed into the 1:2
Output Mode where the data is output on the Dc and Dd
channels at the rate of the input clock.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C ≤ TA ≤ +85°C) temperature range.
Features
■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ 1:2 or 1:4 Selectable Output Demux
■ Clock Phase Adjust for Multiple ADC Synchronization
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock
■ Test pattern
Key Specifications
■ Resolution
■ Max Conversion Rate
■ Bit Error Rate (BER)
■ ENOB @ 748 MHz Input
■ SNR @ 748 MHz
■ Full Power Bandwidth
■ Power Consumption
— Operating
— Power Down Mode
8 Bits
3 GSPS (min)
10-18 (typ)
7.0 Bits (typ)
44 dB (typ)
3 GHz (typ)
1.8 W (typ)
20 mW (typ)
Applications
■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation
Ordering Information
Industrial Temperature Range
(-40°C < TA < +85°C)
ADC083000CIYB
ADC08x3000EB
NS Package
128-Pin Exposed Pad LQFP
Development Board
© 2007 National Semiconductor Corporation 201932
www.national.com
1 page  
Pin Functions
Pin No.
Symbol
31 VBG
126 CalRun
Equivalent Circuit
Description
Bandgap Output Voltage
(Output):Analog - Capable of 100 μA source/sink and can drive
a load up to 80 pF.
Calibration Running
(Output):LVCMOS - This pin is at a logic high when calibration
is running.
32 REXT
34 Tdiode_P
35 Tdiode_N
External Bias Resistor Connection
Analog - Nominal value is 3.3k-Ohms (±0.1%) to ground. See
Section 1.1.1.
Temperature Diode
Analog - Positive (Anode) and Negative (Cathode) for die
temperature measurements. See Section 2.6.2.
5 www.national.com
5 Page 
Symbol
Parameter
Conditions
AC ELECTRICAL CHARACTERISTICS - Sampling Clock
fCLK1
fCLK2
Maximum Input Clock Frequency Sampling rate is 2x clock input
Minimum Input Clock Frequency Sampling rate is 2x clock input
tCYC Input Clock Duty Cycle
500MHz ≤ Input clock frequency ≤ 1.5
GHz (Note 12)
tLC Input Clock Low Time
tHC Input Clock High Time
(Note 11)
(Note 11)
DCLK Duty Cycle
(Note 11)
Typical
(Note 8)
1.7
500
50
333
333
50
tDA
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of Data
tJA Aperture Jitter
tDO
Input Clock to Data Output Delay 50% of Input Clock transition to 50% of
(in addition to Pipeline Delay) Data transition
Dd Outputs
Pipeline Delay (Latency)
(Notes 11, 14)
Db Outputs
Dc Outputs
Da Outputs
AC ELECTRICAL CHARACTERISTICS - Output Clock and Data
tLHT
tHLT
tDS
tSKEWO
LH Transition Time - Differential
HL Transition Time - Differential
Output Delay - Syncronizing
Edge to DCLK
DCLK to Data Output Skew
10% to 90%, CL = 2.5 pF
10% to 90%, CL = 2.5 pF
fCLKIN = 1.5 GHz
fCLKIN = 500 MHz
50% of DCLK transition to 50% of Data
transition, SDR Mode
and DDR Mode, 0° DCLK (Note 11)
tS
Data to DCLK Set-Up Time
DDR Mode, 90° DCLK (Note 11)
tH
DCLK to Data Hold Time
DDR Mode, 90° DCLK (Note 11)
AC ELECTRICAL CHARACTERISTICS - Serial Interface Clock
fSCLK
tSS
tHS
Serial Clock Frequency
(Note 11)
Data to Serial Clock Setup Time (Note 11)
Data to Serial Clock Hold Time (Note 11)
Serial Clock Low Time
Serial Clock High Time
AC ELECTRICAL CHARACTERISTICS - General Signals
tSR
tHR
tPWR
tWU
Setup Time Reset
Hold Time Reset
Pulse Width Reset
PD low to Rated Accuracy
Conversion (Wake-Up Time)
(Note 11)
(Note 11)
(Note 11)
tCAL
tCAL_L
tCAL_H
tCalDly
Calibration Cycle Time
CAL Pin Low Time
CAL Pin High Time
Calibration delay determined by
pin 127
See Figure 9 (Note 11)
See Figure 9 (Note 11)
See Section 1.1.1, Figure 9, (Note 11)
tCalDly
Calibration delay determined by See Section 1.1.1, Figure 9, (Note 11)
pin 127
1.3
0.4
3.1
250
250
TBD
TBD
±50
437
747
100
2.5
1
150
250
1
1.4 x 105
Limits
(Note 8)
1.5
20
80
133
133
45
55
13
14
13.5
14.5
Units
(Limits)
GHz (min)
MHz
% (min)
% (max)
ps (min)
ps (min)
% (min)
% (max)
ns
ps rms
ns
Input Clock
Cycles
ps
ps
ns
ps (max)
ps
ps
MHz
ns (min)
ns (min)
4 ns (min)
4 ns (min)
ps
ps
4 Clock Cyc. (min)
µs
Clock Cycles
80 Clock Cyc. (min)
80 Clock Cyc.(min)
225 Clock Cyc.(min)
231 Clock Cyc.(max)
11 www.national.com
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet ADC083000.PDF ] | |
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