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X1288 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer X1288
Beschreibung RTC Real Time Clock/Calendar/CPU Supervisor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 27 Seiten
X1288 Datasheet, Funktion
®
Data Sheet
April 14, 2006
X1288
FN8102.3
2-WireRTC Real Time
Clock/Calendar/CPU Supervisor with
EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, Seconds and
Hundredths of a Second
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital-frequency adjustment setting to
±30ppm
• CPU Supervisor Functions
— Power-on Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
www.DataSheet4U.com — 128-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
BLOCK DIAGRAM
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 16-Lead SOIC and 14-Lead TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
256K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
I2C is a trademark of Philips. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






X1288 Datasheet, Funktion
X1288
AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
Parameter
Min.
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR
tF
Cb
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
50(1)
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb(1)(2)
20 +.1Cb(1)(2)
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
Max.
400
0.9
300
300
400
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
pF
TIMING DIAGRAMS
Bus Timing
SCL
tSU:STA
SDA IN
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tHD:DAT
SDA OUT
tR
tAA tDH
tSU:STO
tBUF
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
Stop
Condition
tWC
Start
Condition
6 FN8102.3
April 14, 2006

6 Page









X1288 pdf, datenblatt
X1288
(H21 bit) or 0 to 23 (with MIL=1), DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99. The SSEC
register is read-only.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
standard time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisi-
ble by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1288 does not correct
for the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read two power status and two alarm
bits. This register is separate from both the array and
the Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr 7 6 5 4 3
003Fh BAT AL1 AL0 0
Default 0 0 0 0
0
0
2
RWEL
0
10
WEL RTCF
01
BAT: Battery Supply - Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read-only bit and is set/reset
by hardware (X1288 internally). Once the device begins
operating from VCC, the device sets this bit to “0”.
AL1, AL0: Alarm Bits - Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch - Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so
the device is ready for the next operation immediately
after the stop condition. A write to the CCR requires
both the RWEL and WEL bits to be set in a specific
sequence.
WEL: Write Enable Latch - Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit - Volatile
This bit is set to a “1” after a total power failure. This is
a read only bit that is set by hardware (ISL1288 inter-
nally) when the device powers up after having lost all
power to the device (both VCC and VBACK go to 0V).
The bit is set regardless of whether VCC or VBACK is
applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. On power up after a total
power failure, all registers are set to their default
states and the clock will not increment until at least
one byte is written to the clock register. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is
sufficient).
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
12 FN8102.3
April 14, 2006

12 Page





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