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X1228 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer X1228
Beschreibung Real Time Clock/Calendar/CPU Supervisor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 29 Seiten
X1228 Datasheet, Funktion
® NOT RDENaSCtEaEOWESMDhIMSEeELeS1NtIG2D0NE2SD8 FOR
X1228
4K (512 x 8), 2-WireRTC
May 18, 2006
FN8100.4
Real Time Clock/Calendar/CPU
Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to
±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
www.DataSheet4U.com
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I2C*
— 400kHz Data Transfer Rate
• Frequency Output (SW Selectable: Off, 1Hz,
4096Hz, or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 14 Ld SOIC and 14 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






X1228 Datasheet, Funktion
X1228
AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR
tF
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
Min.
50(1)
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb(2)
20 +.1Cb(2)
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
Max.
400
0.9
300
300
400
Units
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
pF
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA IN
SDA OUT
tHD:STA
tSU:DAT
tHD:DAT
tAA tDH
tSU:STO
tBUF
6 FN8100.4
May 18, 2006

6 Page









X1228 pdf, datenblatt
X1228
Table 1. Clock/Control Memory Map (Continued)
Addr.
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Type
Alarm1
(EEPROM)
Alarm0
(EEPROM)
Reg
Name
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
7
0
EDW1
EMO1
EDT1
EHR1
EMN1
ESC1
0
EDW0
EMO0
EDT0
EHR0
EMN0
ESC0
Bit
65 4 3 2 1
0 A1Y2K21 A1Y2K20 A1Y2K13
0
0
0 0 0 0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A1G20 A1G13 A1G12 A1G11
0 A1D21 A1D20 A1D13 A1D12 A1D11
0 A1H21 A1H20 A1H13 A1H12 A1H11
A1M22 A1M21 A1M20 A1M13 A1M12 A1M11
A1S22 A1S21 A1S20 A1S13 A1S12 A1S11
0 A0Y2K21 A0Y2K20 A0Y2K13
0
0
0 0 0 0 DY2 DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0 0 A0G20 A0G13 A0G12 A0G11
0 A0D21 A0D20 A0D13 A0D12 A0D11
0 A0H21 A0H20 A0H13 A0H12 A0H11
A0M22 A0M21 A0M20 A0M13 A0M12 A0M11
A0S22 A0S21 A0S20 A0S13 A0S12 A0S11
0 (optional)
A1Y2K10
DY0
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
A0G10
A0D10
A0H10
A0M10
A0S10
Range
19/20
0-6
1-12
1-31
0-23
0-59
0-59
19/20
0-6
1-12
1-31
0-23
0-59
0-59
20h
00h
00h
00h
00h
00h
00h
20h
00h
00h
00h
00h
00h
00h
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1228 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
Date of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
standard time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisi-
ble by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1228 does not correct
for the leap year in the year 2100.
12 FN8100.4
May 18, 2006

12 Page





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