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PDF AM50DL128CG Data sheet ( Hoja de datos )

Número de pieza AM50DL128CG
Descripción Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM
Fabricantes AMD 
Logotipo AMD Logotipo



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No Preview Available ! AM50DL128CG Hoja de datos, Descripción, Manual

Am50DL128CG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
www.DataSheet4U.com
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 26880 Revision A Amendment +2 Issue Date November 7, 2002

1 page




AM50DL128CG pdf
PRELIMINARY
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 58
pSRAM Power on and Deep Power Down . . . . . 58
Figure 32. Deep Power-down Timing.............................................. 58
Figure 33. Power-on Timing............................................................ 58
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 59
Figure 34. Read Address Skew ...................................................... 59
Figure 35. Write Address Skew...................................................... 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60
FTA088—88-Ball Fine-Pitch Grid Array 11.6 x 8 mm ............. 60
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
4
Am50DL128CG
November 7, 2002

5 Page





AM50DL128CG arduino
PRELIMINARY
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
10
Am50DL128CG
November 7, 2002

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