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PDF AM41PDS3224D Data sheet ( Hoja de datos )
| Número de pieza | AM41PDS3224D | |
| Descripción | Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM | |
| Fabricantes | AMD | |
| Logotipo |  |
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Am41PDS3224D
Data Sheet
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Publication Number 26085 Revision A Amendment +1 Issue Date May 13, 2003
1 page  
PRELIMINARY
Write Cycle ............................................................................. 52
Figure 30. SRAM Write Cycle—WE# Control ................................. 52
Figure 31. SRAM Write Cycle—CE1#s Control .............................. 53
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ................ 54
Flash Erase And Programming Performance . . 55
Flash Latchup Characteristics . . . . . . . . . . . . . . 55
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 56
Figure 33. CE1#s Controlled Data Retention Mode....................... 56
Figure 34. CE2s Controlled Data Retention Mode......................... 56
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 57
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (February 18, 2002) .............................................. 58
Revision A+1 (May 13, 2002) ................................................. 58
4
Am41PDS3224D
May 13, 2002
5 Page 
PRELIMINARY
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Tables 1–2 list the device bus opera-
tions, the inputs and control levels they require, and
the resulting output. The following subsections de-
scribe each of these operations in further detail.
Operation
(Notes 1, 2)
Read from Flash
Write to Flash
Standby
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = VCC
CE#f CE1#s CE2s OE# WE# SA
Addr.
LB#s
(Note 3)
UB#s RESET#
(Note 3)
WP#/ACC
(Note 4)
HX
L
X
LH X
L
AIN
X
X
H
L/H
HX
L
X
HL
X
L
AIN
X
X
H (Note 4)
VCC ±
0.3 V
H
X
X
XX
X
L
X
X
X
VCC ±
0.3 V
H
DQ7–
DQ0
DOUT
DIN
High-Z
DQ15–
DQ8
DOUT
DIN
High-Z
Output Disable
HH X
X
L LH
HH X
X
LX
H
XL
L/H High-Z High-Z
Flash Hardware
Reset
HX
X
XX
X
X
XL
XX
L
L/H High-Z High-Z
Sector Protect
(Note 5)
HX
SADD,
L
X
L
HL
X
A6 = L,
A1 = H,
X
A0 = L
HX
SADD,
Sector Unprotect
(Note 5)
L
X
L
HL
X
A6 = H,
A1 = H,
X
A0 = L
Temporary Sector
Unprotect
X
H
X
X
XX
X
L
X
X
X VID
L/H DIN X
X
VID
(Note 6)
DIN
X
X
VID
(Note 6)
DIN High-Z
LL
Read from SRAM
H
L
H LH X
AIN
H
L
H
LH
LL
Write to SRAM
H
L
H XL X
AIN
H
L
H
LH
DOUT
DOUT
X High-Z DOUT
DOUT High-Z
DIN DIN
L/H
High-Z
DIN
DIN High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 9–11 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends
on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If
WP#/ACC = VHH, all sectors will be unprotected.
10
Am41PDS3224D
May 13, 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM41PDS3224D.PDF ] | |
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