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PDF AM41DL32X8G Data sheet ( Hoja de datos )
| Número de pieza | AM41DL32X8G | |
| Descripción | Simultaneous Read/Write Flash Memory | |
| Fabricantes | AMD | |
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Am41DL32x8G
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25558 Revision A Amendment +1 Issue Date September 5, 2002
1 page  
PRELIMINARY
Figure 21. Back-to-back Read/Write Cycle Timings ....................... 50
Figure 22. Data# Polling Timings (During Embedded Algorithms).. 50
Figure 23. Toggle Bit Timings (During Embedded Algorithms)....... 51
Figure 24. DQ2 vs. DQ6.................................................................. 51
Temporary Sector/Sector Block Unprotect ............................. 52
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 52
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 53
Alternate CE#f Controlled Erase and Program Operations .... 54
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 55
SRAM Read Cycle .................................................................. 56
Figure 28. SRAM Read Cycle—Address Controlled....................... 56
Figure 29. SRAM Read Cycle......................................................... 57
SRAM Write Cycle .................................................................. 58
Figure 30. SRAM Write Cycle—WE# Control ................................ 58
Figure 31. SRAM Write Cycle—CE1#s Control ............................. 59
Figure 32. SRAM Write Cycle—UB#s and LB#s Control............... 60
Flash Erase And Programming Performance ........................ 61
Flash Latchup Characteristics. . . . . . . . . . . . . . . 61
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 61
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 61
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 62
Figure 33. CE1#s Controlled Data Retention Mode....................... 62
Figure 34. CE2s Controlled Data Retention Mode......................... 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 63
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64
Revision A (October 25, 2001) ............................................... 64
Revision A+1 (September 5, 2002) ........................................ 64
4
Am41DL32x8G
September 5, 2002
5 Page 
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Tables 1 through 3 list the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections de-
scribe each of these operations in further detail.
10
Am41DL32x8G
September 5, 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM41DL32X8G.PDF ] | |
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