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PDF AM29LV652D Data sheet ( Hoja de datos )
| Número de pieza | AM29LV652D | |
| Descripción | Uniform Sector Flash Memory | |
| Fabricantes | AMD | |
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Am29LV652D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new designs, S29GL128N
supersedes Am29LV652D. Please refer to the S29GL-N family data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes
only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 24961 Revision E Amendment 5 Issue Date May 5, 2006
1 page  
DATA SHEET
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV652D Device Bus Operations ................................9
VersatileIO™ (VIO) Control ....................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Accelerated Program Operation .......................................... 10
Autoselect Functions ........................................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table for CE# ..........................................11
Table 3. Sector Address Table for CE2# ........................................15
Autoselect Mode ..................................................................... 19
Table 4. Am29LV652D Autoselect Codes, (High Voltage Method) 19
Sector Group Protection and Unprotection ............................. 20
Table 5. Sector Group Protection/Unprotection Address Table .....20
Temporary Sector Group Unprotect ....................................... 21
Figure 1. Temporary Sector Group Unprotect Operation................ 21
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 22
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit ......................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 6. CFI Query Identification String .......................................... 23
System Interface String................................................................... 24
Table 8. Device Geometry Definition .............................................. 24
Table 9. Primary Vendor-Specific Extended Query ........................ 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Byte Program Command Sequence ....................................... 26
Unlock Bypass Command Sequence .................................. 26
Figure 3. Program Operation .......................................................... 27
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 28
Figure 4. Erase Operation............................................................... 29
Table 10. Am29LV652D Command Definitions ..............................30
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 5. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 6. Toggle Bit Algorithm........................................................ 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 11. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ..................... 35
Figure 8. Maximum Positive Overshoot Waveform....................... 35
DC Characteristics
(for two Am29LV065 devices) . . . . . . . . . . . . . . . 36
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 37
Figure 10. Typical ICC1 vs. Frequency ............................................ 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup.................................................................... 38
Table 12. Test Specifications ......................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38
Key to Switching Waveforms. . . . . . . . . . . . . . . . 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 13. Read Operation Timings ............................................... 39
Hardware Reset (RESET#) .................................................... 40
Figure 14. Reset Timings ............................................................... 40
Erase and Program Operations .............................................. 41
Figure 15. Program Operation Timings.......................................... 42
Figure 16. Accelerated Program Timing Diagram.......................... 42
Figure 17. Chip/Sector Erase Operation Timings .......................... 43
Figure 18. Data# Polling Timings (During Embedded Algorithms). 44
Figure 19. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 20. DQ2 vs. DQ6................................................................. 45
Temporary Sector Unprotect .................................................. 46
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 46
Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 47
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 49
Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50
Input/Output Capacitance . . . . . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FSA063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm
package .................................................................................. 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
May 5, 2006 24961A5
Am29LV652D
3
5 Page 
DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV652D Device Bus Operations
Operation
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
CE#
(Note 1)
OE#
LL
LH
LH
VCC ± 0.3 V
L
X
H
XX
WE# RESET#
HH
LH
LH
X VCC ± 0.3 V
HH
XL
ACC
X
X
VHH
H
X
X
Addresses
(Note 2)
AIN
AIN
AIN
X
X
X
DQ0–DQ7
DOUT
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
Sector Group Protect (Note 4)
Sector Group Unprotect
(Note 4)
Temporary Sector Group
Unprotect
L
L
X
HL
HL
XX
VID
VID
VID
X
SA, A6 = L,
A1 = H, A0 = L
(Note 3)
X
SA, A6 = H,
A1 = H, A0 = L
(Note 3)
X AIN (Note 3)
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at
the same time.
2. Addresses are A22:A0. Sector addresses are A22:A16.
3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
5. All sectors are unprotected when shipped from the factory.
VersatileIO™ (VIO) Control
The VersatileIO (VIO) control allows the host system to
set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data in-
puts to the same voltage level that is asserted on VIO.
This allows the device to operate in a 3 V or 5 V sys-
tem environment as required. For voltage levels below
3 V, contact an AMD representative for more informa-
tion.
For example, a VI/O of 4.5–5.0 volts allows for I/O at
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive CE# or CE2# and OE# to VIL. CE# or CE2# is the
power control and selects the device. OE# is the out-
put control and gates array data to the outputs. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
May 5, 2006 24961A5
Am29LV652D
9
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