Datenblatt-pdf.com


EM6635 Schematic ( PDF Datasheet ) - EM Microelectronic

Teilenummer EM6635
Beschreibung Low Power Microcontroller
Hersteller EM Microelectronic
Logo EM Microelectronic Logo 




Gesamt 30 Seiten
EM6635 Datasheet, Funktion
EM MICROELECTRONIC - MARIN SA
EM6635
Low Power Microcontroller with RC and 32kHz oscillators
and 9 high drive outputs
Features
32’768Hz crystal oscillator
500kHz RC Oscillator (no external component)
External clock (metal option)
9 High drive outputs: up to 20mA
Melody generator with 255 programmable
frequencies
True Low Power: 1.5uA active mode
0.4uA halt mode
@ 1.55V, 32kHz, 25°C
Low Supply Voltage 1.2V to 3.6V
Max. 14 Inputs with selectable debouncers; Port P1,
P2, P6, P70, P71
Max. 15 outputs (9 I/O High drive outputs); Port P3,
P4, P6, P70, P71, P72
Mask ROM 4096 x 16bits
RAM 256 x 4bits
2 clocks per instruction cycle
72 basic instructions
2 outputs; Reset OUT, Buzzer OUT
2 timers 8bits
2 x 4 bits BCD counters
Event counter 3bits
Prescaler down to 1Hz (crystal =32kHz), readable by
CPU in 2 ranges
Serial Port as selectable configuration of Port 5
18 Interrupts: 12 internal, 6 external
Voltage Level Detector, 3 levels software selectable
Die form and MLF2, 40 pin (Micro Lead Frame)
package
Description
The EM6635 is a low voltage, low power microcontroller
containing 9 integrated high-drive outputs able to provide
up to 20mA. It is ideal for use in applications in which one
must drive devices such as motor drivers, small stepping
motors, LEDs, triacs, external EEPROM or other ICs in
the system.
EM6635 has both a 32kHz crystal oscillator and a
500kHz RC oscillator without external component, as well
as an external clock to be driven up to 4MHz.
The CPU operating clock can be switched from crystal to
RC oscillator for high-speed operation.
It has a frequency/melody generator with 255
programmable frequencies for quality buzzer.
The EM6635 contains the equivalent of 8kB mask ROM
and the RAM has a capacity of 256x4 bits.
It also has a power-on reset, watchdog timer, 2 timers
8bits, 2 BCD counters, 3bits event counter, 4 wire serial
port 8bits and several clock functions.
Copyright 2002, EM Microelectronic-Marin SA
Figure 1. Architecture
Crystal
Oscillator
32kHz
or
External
clock
ROM
4096 x 16Bits
RAM
256 x 4Bits
RC Oscillator
500kHz
Watch Dog
timer
Timer 1
VLD 3levels
Frequency
Doubler
Power Supply
Voltage reg.
Reset
Logic
Core
EM6600
Timer 2
BCD
Counter
Frequency
Generator
Interrupt
Controller
Port 1
Port 2
Port 3
Port 4 Port 5
Port 6
Port 7
0123 0123 0123 0123 0123 0123 0123
High Drive Output
Serial or
parallel port
2 : High Drive Output
3 : Buzzer out
Figure 2. Typical application
SIO
+VBAT
Stepping Motors
P4
P5
P1
P2
P3 P72
EM6635
VBAT
PI E Z O
BZ
CENV
P6
P70,P71
+VBAT
Reset IN
QIN QOUT
VSS
32kHz Xtal
Reset Out
VRR
C VRR
Applications
Watch & clock
Timer / sports timing devices
Security / industrial
Toys
Sensor interface
03/03 REV. B
1 www.emmicroelectronic.com






EM6635 Datasheet, Funktion
EM6635
Terminal
VBAT
All Pad
input &
output
buffers,
SVLD
_
+
Ref.
Logic
MVreg
OP16B
OP16A
RFIL
Terminal
VRR
CPU, ROM, RAM
Peripheral Logic,
Oscillator, POR
Fig.3: Power Supply Principle
5. Reset
The EM6635 has 4 reset sources:
- the Power On Reset
- external reset input
- reset by input combination
- watchdog timer reset
If one of these reset sources becomes active, a system reset is generated. All registers are set to their corresponding initial
values and the program counter of the CPU is set to H000.
If the EM6635 is in HALT mode, it is reset to active mode.
An internal Cold Start delay is triggered from the system reset, which holds the CPU in reset state until its time out. This
ensures that the crystal oscillator can settle to stable oscillation.
The Cold Start delay time can be selected by mask option OP-2.
The Cold Start can be disabled by input P22 AND P23 = 1, if this input combination is applied longer than the duration of
SYSRES signal (SYSRES terminates after the oscillator start time plus 10 valid clock time periods.) If this condition
becomes active after the SYSRES has changed to low, but during an active Cold Start, the Cold Start will be stopped
immediately. During the CPURES (corresponds to the Cold Start, after system starts on Xtal oscillator), pull down
transistors are active at all port inputs.
Note that all 4 reset sources are triggering the Cold Start delay.
RESETIN
Schmitt Trigger
DisInpResN
P13
P22 Debouncer
P23
System
Reset
SYSRES
Ck1Hz
DisWD
Watch Dog Timer
Power On
Reset
OP1A
OP1B
OP3A
OP3B
OP9A
OP9B
Fig.4: Reset Structure
Copyright 2002, EM Microelectronic-Marin SA
6
OP2ABCD
CkCS
OP2E
Set
Cold Start
Timer
Reset
CPURES
03/03 REV. B
www.emmicroelectronic.com

6 Page









EM6635 pdf, datenblatt
EM6635
8.3 Input/Output Port P3
The port P3 is a 4bit input/output port with high current drive capability, e.g. for watch motor driver.
The port direction is controlled by the "PIO43 Ctl" register at address H52. The bit "P3-Dir" (bit 0, address H52) defines the
direction of P30 to P32 commonly, whereas "P33-Dir" (bit 2, address H52) defines the individual direction of P33. A "1" level
of the direction bit configures the corresponding port to be output, a "0" level defines it as input.
If the port P3 is configured as output, a write access to the P3 data register (address H50) stores the data into the internal
port data register and the data appear at the corresponding port terminals. The port data register is only written when the
port bit is output.
If a port P3 bit is read when the port is output, the data comes from the port output register. When the port is input, the data
is read from the port terminal (output buffer in high impedance). The data LSB is at bit 0, the MSB at bit 3.
After system reset, the direction is input, the output data register contains "0000".
At port P3, no pull up or pull down element is available during normal operation.
Note: Extra pull down transistors are active at this port during the CPURES signal.
8.3.1 Frequency Output
With mask option OP-18, the function of the output P33 can be modified directly or under CPU control. If OP-18A is chosen,
the CPU can select with “ENFOut” set to “1”, that the port P33 is set to output, but disconnected from its data register.
Instead, it is configured as frequency output.
The output frequency is defined by the serial clock selection bits "SelSIOClk0, “1" in SIO-Ctl1(bit 3, address H72),
independent of the "EnSIO" state, which enables the serial interface, configurated at port P5.
If the frequency output is set to 32 kHz, the output signal is the system clock from the quartz oscillator. In this case, the
duty cycle is subject to higher tolerances than in case of the other possible output frequencies. If option OP-18B is chosen,
the output P33 is always output for Fout, independently of the setting “ENFOut”.
SelSIOClk1
0
0
1
1
SelSIOClk0
0
1
0
1
Frequency at Fout = P33
according to OP-8: 1kHz - 512Hz - 128Hz - 32Hz
32kHz
16kHz
4kHz
8.3.2 Synchron Mode (Special Motor Mode)
If timer 1 is set to Synchron Mode by "SynMode" = "1", the port P3 operates in a special way, optimised to facilitate driving
of watch motors.
The port must be set to output by the "PIO43-Ctl" register bits "P3-Dir" and/or "P33-Dir". An eventually "EnFOut"
configuration has priority over Synchron Mode setting for port P33.
The Synchron Mode can work with the P30 to P32 bits alone or together with P33, if this port is also set to output and not
frequency output.
Function:
As long as timer1 is not actively counting (its "TimerOn" signal is "0"), all the selected port P3 outputs are in "1" state.
During active timer 1 counting, the selected P3 outputs correspond to the content of the port P3 output data register. The
port state returns to all "1" after timer 1 has finished.
In this way, a predefined pattern loaded in the data output register appears synchronously with the timer 1 action for the
programmed time at the P3 output, driving e.g. a stepper motor. (See also timer 1 description, Synchron Mode).
CPU Access Format:
Register
Port P3
Add Hex
50
Add Dec
80
PIO43 Ctl 52 82
W
R
W
R
bit3
P33 (Fout)
P33 (Fout)
(P43-Dir)
(P43-Dir)
bit2
P32
P32
P33-Dir
P33-Dir
bit1
P31
P31
(P4-Dir)
(P4-Dir)
bit0
P30
P30
P3-Dir
P3-Dir
Copyright 2002, EM Microelectronic-Marin SA
12
03/03 REV. B
www.emmicroelectronic.com

12 Page





SeitenGesamt 30 Seiten
PDF Download[ EM6635 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
EM6635Low Power MicrocontrollerEM Microelectronic
EM Microelectronic

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche