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EM6607 Schematic ( PDF Datasheet ) - EM Microelectronic

Teilenummer EM6607
Beschreibung Ultra-low power microcontroller
Hersteller EM Microelectronic
Logo EM Microelectronic Logo 




Gesamt 30 Seiten
EM6607 Datasheet, Funktion
R
EM MICROELECTRONIC - MARIN SA
EM6607
Ultra-low power microcontroller
with 4 high drive outputs
Features
‰ Low Power typical 1.8µA active mode
typical 0.5µA standby mode
typical 0.1µA sleep mode
@ 1.5V, 32kHz, 25 °C
‰ Low Voltage 1.2 to 3.3 V
‰ ROM
2k × 16 (Mask Programmed)
‰ RAM
96 × 4 (User Read/Write)
‰ 2 clocks per instruction cycle
‰ RISC architecture
‰ 5 software configurable 4-bit ports
‰ 1 High drive output port
‰ Up to 20 inputs
(5 ports)
‰ Up to 16 outputs
(4 ports)
‰ buzzer three tone
‰ Serial Write buffer – SWB
‰ Supply Voltage level detection (SVLD).
‰ Analogue and timer watchdog
‰ 8 bit timer / event counter
‰ Internal interrupt sources (timer, event counter,
prescaler)
‰ External interrupt sources (portA + portC)
Description
The EM6607 is a single chip low power, mask
programmed CMOS 4-bit microcontroller. It contains
ROM, RAM, watchdog timer, oscillation detection circuit,
combined timer / event counter, prescaler, voltage level
detector and a number of clock functions. Its low voltage
and low power operation make it the most suitable
controller for battery, stand alone and mobile equipment.
The EM6607 microcontroller is manufactured using EM’s
Advanced Low Power CMOS Process.
In 24 Pin package it is direct replacement for EM6603.
Typical Applications
‰ sensor interfaces
‰ domestic appliances
‰ clocks
‰ security systems
‰ bicycle computers
‰ automotive controls
‰ TV & audio remote controls
‰ measurement equipment
‰ R/F and IR. control
‰ motor driving
Figure 1. Architecture
32KHz
Crystal Osc
VLD 3 Levels
Prescaler
ROM
2k X 16Bit
RAM
96 X 4Bit
V VDD REG
V SS
Power
Supply
Power on
Reset
8-Bit Event
Count/Timer
Core
EM6600
3 Tone
Buzzer
Interrupt
Controller
Watchdog
Timer
Port A
0 123
Port B
0 123
Port C
0 123
Serial Write
Buffer
Port D
Port E
0123 0 123
High Drive
Outputs
Clk Buzzer
Data
Figure 2. Pin Configuration
PA0 1
24 VDD
PA1 2
23 VREG
PA2 3
22 RESET
PA3 4
21 PD3
PB0 5
20 PD2
PB1
PB2
6
7
EM6607
19 PD1
18 PD0
PB3 8
17 PC3
TEST 9
16 PC2
QOUT 10
15 PC1
QIN11
14 PC0
VSS12
13 STB/RST
PA0 1
28 VDD
PA1 2
27 VREG
PA2 3
26 RESET
PA3 4
25 PE3
PE0 5
24 PD3
PB0 6
23 PD2
PB1 7 EM6607 22 PD1
PB2 8
21 PD0
PB3 9
20 PE2
PE1 10
19 PC3
TEST 11 EM6680 18 PC2
QOUT 12
17 PC1
QIN 13
16 PC0
VSS 14
15 STB/RST
(TS)SOP-24
(TS)SOP-28
Copyright © 2005, EM Microelectronic-Marin SA
1
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EM6607 Datasheet, Funktion
R
Figure 3. Typical Configuration: VDD 1.4V up to 3.3V
EM6607
VDD V. Regulator
VREG
+C
C+
VSS
Logic
ROM
RAM
POR
SLEEP
QIN QOUT
Oscillator
PA
PB
I/O Drivers
SVLD
SWB
PC
PD
PE
Reset
Strb/Rst
Test
Figure 4. Typical Configuration: VDD 1.2V up to 1.8V
+C
VDD
VREG
V. Regulator
Logic
ROM
RAM
POR
VSS
SLEEP
QIN QOUT
Oscillator
PA
PB
I/O Drivers
SVLD
SWB
PC
PD
PE
Reset
Strb/Rst
Test
Copyright © 2005, EM Microelectronic-Marin SA
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6 Page









EM6607 pdf, datenblatt
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EM6607
5 Oscillator
A built-in crystal oscillator circuit generates the system-operating clock for the CPU and peripheral circuits from an externally
connected crystal (typ. 32.768kHz) and trimmer capacitor (from Qin tw. VSS). The regulated voltage, VREG, supplies the
oscillator circuit. In SLEEP mode the oscillator is stopped.
With Fout bit in PA3cnt register we can put the system 32.768 Hz frequency on STB/RST pin as output.
5.1 Prescaler
The input to the prescaler is the system clock signal. The
prescaler consists of a fifteen (15) element divider chain
which delivers clock signals for the peripheral circuits such
as the timer/counter, buzzer, I/O debouncers and edge
detectors, as well as generating prescaler interrupts.
Table 8. Prescaler interrupts source
Interrupt frequency
mask(no interrupt)
1 Hz
8 Hz
32 Hz
PSF1
0
0
1
1
PSF0
0
1
0
1
The frequency of prescaler interrupts is software selectable, as shown in Table 8.
Table 9.
Bit
3
2
1
0
Prescaler control register - PRESC
Name
MTim
PRST
PSF1
PSF0
Reset
0
-
0
0
R/W
R/W
R/W
R/W
R/W
Description
Timer/Counter Interrupt Mask
Prescaler reset
Prescaler Interrupt select 1
Prescaler Interrupt select 0
6 Watchdog timer
If for any reason the CPU crashes, then the watchdog timer can detect this situation and output a system reset signal. This
function can be used to detect program overrun. For normal operation the watchdog timer must be reset periodically by
software at least once every three seconds (CLK = 32kHz) or a system reset signal is generated to CPU and periphery. The
watchdog is active during STANDBY. Setting the NoWD bit to 1 in the Option register deactivates the watchdog-reset function.
In worst case because of prescaler reset function WD time-out can come down to 2 seconds.
Writing 1 to the WDRST bit resets the watchdog timer. Writing 0 to WDRST has no effect.
The watchdog timer also operates in STANDBY mode. It is therefore necessary to reset it if this mode continues for more than
three seconds. One method to do so is to use the prescaler 1Hz interrupt such, that the watchdog is reset every second.
Table 10.
Bit
3
2
1
0
Watchdog register - WD
Name
WDRST
Slmask
WD1
WD0
Reset
-
-
0
0
R/W
R/W
R/W
R
R
Description
Watchdog timer reset
SLEEP mask bit
WD Timer data 1/4 Hz
WD Timer data 1/2 Hz
Copyright © 2005, EM Microelectronic-Marin SA
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