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EM6603 Schematic ( PDF Datasheet ) - EM Microelectronic

Teilenummer EM6603
Beschreibung Ultra Low Power Multi I/O Microcontroller
Hersteller EM Microelectronic
Logo EM Microelectronic Logo 




Gesamt 30 Seiten
EM6603 Datasheet, Funktion
EM MICROELECTRONIC - MARIN SA
EM6603
Ultra Low Power Multi I/O Microcontroller
Features
Low Power - typical 1.8µA active mode
- typical 0.35µA standby mode
- typical 0.1µA sleep mode
@ 1.5V, 32kHz, 25 °C
Low Voltage - 1.2 to 3.6 V
buzzer - three tone
ROM - 2k × 16 (Mask Programmed)
RAM - 96 × 4 (User Read/Write)
2 clocks per instruction cycle
RISC architecture
4 software configurable 4-bit ports
Up to 16 inputs (4 ports)
Up to 12 outputs (3 ports)
Serial (Output) Write buffer - SWB
Voltage level detection
Analogue watchdog
Timer watchdog
8 bit timer / event counter
Internal interrupt sources (timer, event
counter, prescaler, SWB)
External interrupt sources (portA + portC)
Description
The EM6603 is an advanced single chip low cost,
mask programmed - CMOS 4-bit microcontroller. It
contains ROM, RAM, watchdog timer, oscillation
detection circuit, combined timer / event counter,
prescaler, voltage level detector and a number of
clock functions. Its low voltage and low power
operation make it the most suitable controller for
battery, stand alone and mobile equipment. The
EM66XX series is manufactured using EM
Microelectronic’s Advanced Low Power CMOS
Process.
Typical Applications
sensor interfaces
domestic appliances
security systems
bicycle computers
automotive controls
TV & audio remote controls
measurement equipment
R/F and IR. control
Figure 1.Architecture
Figure 2.Pin Configuration
Copyright 2002, EM Microelectronic-Marin SA
1
03/02 REV. G/439
www.emmicroelectronic.com






EM6603 Datasheet, Funktion
EM6603
3 Reset
To initialize the EM6603, a system RESET must be executed. There are four methods of doing this:
(1) Initial RESET from the oscillation detection circuit.
(2) External RESET from the RESET PIN.
(3) External RESET by simultaneous high input to terminals PA0..PA3.
(Combinations defined by metal option)
(4) Watchdog RESET (software option).
During any of these RESET’s the STB/RST output pin is high.
Figure 5.System reset generation
3.1 Oscillation detection circuit
At power on, the built-in voltage regulator starts to follow the supply voltage until Vdd becomes higher than Vreg.
Since it is Vreg which supplies the oscillator and this needs time to stabilise, Power-On-Reset with the oscillation
detection circuit therefore counts the first 32768 oscillator clocks after power-on and holds the system in RESET.
The system will consequently remain in RESET for at least one second after power up.
After power up the Analogue Watchdog circuit monitors the oscillator. If it stops for any reason other then SLEEP
mode, then a RESET is generated and the STB/RST pin is driven high.
3.2 Reset Pin
During active or STANDBY mode the RESET terminal has a debouncer to reject noise and therefore must be
active high for at least 2ms or 16ms (CLK = 32kHz) - software selectable by DebCK in CIRQD register. (see
Table 31)
At power on, or when cancelling SLEEP mode, the debouncer is not active and so RESET must satisfy the filter
time constant (typ. 1µsec) such that the RESET must be active high for at least 2µsec.
Copyright 2002, EM Microelectronic-Marin SA
6
03/02 REV. G/439
www.emmicroelectronic.com

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EM6603 pdf, datenblatt
EM6603
6.5 PortC
This port can be configured as either input or output (not bitwise selectable). When in input mode it implements
the identical interrupt functions as PortA. The PortC register is used to read data when input mode and to write
data when in output mode. Input mode is set by writing 0 to the I/O control bit CIOPC in register CPIOB and the
input becomes high impedance. On each terminal Pull-Up/Down resistor can be selected by metal option which
are active only when selected as input.
The output mode is selected by writing 1 to CIOPC bit, and the terminal follows the bits in the PortC register.
When PortC is used as an input, interrupt functions as described for PortA can be enabled. Input to the interrupt
logic can be direct or via a debounced input. With the debPCN bit at 0 in the Option register all the PortC inputs
are debounced and with the debPCN bit at 1 none of the PortC inputs are debounced. MPortC is the interrupt
mask register for this port and IRQpC is the portC interrupt request register. See also section 9.
By writing the PA&C bit in the CPIOB data register it is
possible to combine PortA and PortC interrupt
requests (logic AND) as shown in Table 16.
At initial reset, the CPIOC control register is set to 0,
and the port is in input mode. The MPortC register is
also set to 0, therefore disabling interrupts.
6.6 PortC registers
Table 16.Ports A&C Interrupt Request
IRQPA IRQPC PA&C Request to CPU
0 0 X No
0 1 0 Yes
1 0 0 Yes
1 1 0 Yes
0 1 1 No
1 0 1 No
1 1 1 Yes
Table 17.PortC input/output register - PortC
Bit Name
3 PC3
2 PC2
1 PC1
0 PC0
Reset
-
-
-
-
R/W
R/W
R /W
R/W
R /W
Table 18.PortC Interrupt request register - IRQpC
Bit Name
Reset
R/W
3
IRQpc3
0
R
2
IRQpc2
0
R
1
IRQpc1
0
R
0
IRQpc0
0
R
Table 19.PortC interrupt mask register - MportC
Bit Name
3 MPC3
2 MPC2
1 MPC1
0 MPC0
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
PC3 I/O data
PC2 I/O data
PC1 I/O data
PC0 I/O data
Description
input PC3 interrupt request flag
input PC2 interrupt request flag
input PC1 interrupt request flag
input PC0 interrupt request flag
Description
interrupt mask for input PC3
interrupt mask for input PC2
interrupt mask for input PC1
interrupt mask for input PC0
Copyright 2002, EM Microelectronic-Marin SA
12
03/02 REV. G/439
www.emmicroelectronic.com

12 Page





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