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CED4279 Schematic ( PDF Datasheet ) - CET

Teilenummer CED4279
Beschreibung Dual Enhancement Mode Field Effect Transistor
Hersteller CET
Logo CET Logo 




Gesamt 7 Seiten
CED4279 Datasheet, Funktion
CED4279/CEU4279
Dual Enhancement Mode Field Effect Transistor (N and P Channel)
FEATURES
40V , 14A , RDS(ON) = 32m@VGS = 10V.
RDS(ON) = 46m@VGS = 4.5V.
-40V , -9A , RDS(ON) = 72m@VGS = 10V.
RDS(ON) = 110m@VGS = 4.5V.
Super high dense cell design for extremely low RDS(ON).
G1
High power and current handing capability.
Lead free product is acquired.
TO-252-4L package.
S1
G1
S2
G2
D1/D2
CEU SERIES
TO-252-4L
D1/D2
G2
S1
S2
ABSOLUTE MAXIMUM RATINGS Tc = 25 C unless otherwise noted
Parameter
Symbol
N-Channel P-Channel
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous e
Drain Current-Pulsed a
Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
VDS 40 40
VGS ±20 ±20
ID e 14 -9
IDM 56 -36
10.4
PD 0.08
Operating and Store Temperature Range
TJ,Tstg
-55 to 150
Units
V
V
A
A
W
W/ C
C
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
RθJC
RθJA
Limit
12
50
Units
C/W
C/W
Details are subject to change without notice .
1
Rev 2. 2007.Jan
http://www.cetsemi.com






CED4279 Datasheet, Funktion
N-CHANNEL
5 VDS=20V
ID=6A
4
3
2
1
0
0 2 4 6 8 10 12
Qg, Total Gate Charge (nC)
Figure 13. Gate Charge
P-CHANNEL
5 VDS=20V
ID=4.5A
4
3
2
1
0
0123456
Qg, Total Gate Charge (nC)
Figure 15. Gate Charge
CED4279/CEU4279
102
RDS(ON)Limit
101
100
1ms
10ms
100ms
DC
5
10-1
TC=25 C
TJ=150 C
10-2 Single Pulse
10-2 10-1 100 101 102
VDS, Drain-Source Voltage (V)
Figure 14. Maximum Safe
Operating Area
102
RDS(ON)Limit
101
1ms
10ms
100ms
100 DC
10-1
TC=25 C
TJ=150 C
10-2 Single Pulse
10-2 10-1 100 101 102
-VDS, Drain-Source Voltage (V)
Figure 16. Maximum Safe
Operating Area
6

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