Datenblatt-pdf.com


AD9861 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9861
Beschreibung Mixed-Signal Front-End (MxFE-TM) Baseband Transceiver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9861 Datasheet, Funktion
Mixed-Signal Front-End (MxFE) Baseband
Transceiver for Broadband Applications
AD9861
FEATURES
Receive path includes dual 10-bit analog-to-digital
converters with internal or external reference, 50 MSPS
and 80 MSPS versions
Transmit path includes dual 10-bit, 200 MSPS digital-to-
analog converters with 1×, 2×, or 4× interpolation and
programmable gain control
Internal clock distribution block includes a programmable
phase-locked loop and timing generation circuitry,
allowing single-reference clock operation
20-pin flexible I/O data interface allows various interleaved
or noninterleaved data transfers in half-duplex mode and
interleaved data transfers in full-duplex mode
Configurable through register programmability or
optionally limited programmability through mode pins
Independent Rx and Tx power-down control pins
64-lead LFCSP package (9 mm × 9 mm footprint)
3 configurable auxiliary converter pins
APPLICATIONS
Broadband access
Broadband LAN
Communications (modems)
GENERAL DESCRIPTION
The AD9861 is a member of the MxFE family—a group of
integrated converters for the communications market. The
AD9861 integrates dual 10-bit analog-to-digital converters
(ADC) and dual 10-bit digital-to-analog converters (TxDAC®).
Two speed grades are available, -50 and -80. The -50 is opti-
mized for ADC sampling of 50 MSPS and less, while the -80 is
optimized for ADC sample rates between 50 MSPS and 80 MSPS.
The dual TxDACs operate at speeds up to 200 MHz and
include a bypassable 2× or 4× interpolation filter. Three
auxiliary converters are also available to provide required
system level control voltages or to monitor system signals. The
AD9861 is optimized for high performance, low power, small
form factor, and to provide a cost-effective solution for the
broadband communication market.
The AD9861 uses a single input clock pin (CLKIN) to generate
all system clocks. The ADC and TxDAC clocks are generated
within a timing generation block that provides user programma-
ble options such as divide circuits, PLL multipliers, and switches.
A flexible, bidirectional 20-bit I/O bus accommodates a variety
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
VIN+A
VIN–A
VIN+B
VIN–B
IOUT+A
IOUT–A
IOUT+B
IOUT–B
FUNCTIONAL BLOCK DIAGRAM
ADC
ADC
DATA
MUX
AND
LATCH
Rx DATA
DAC
DAC
LOW-PASS
INTERPOLATION
FILTER
I/O
INTERFACE
CONFIGURATION
BLOCK
DATA
LATCH
AND
DEMUX
Tx DATA
I/O
INTERFACE
CONTROL
FLEXIBLE
I/O BUS
[0:19]
AUX
ADC
AUX
DAC
AUX
DAC
AUX
ADC
AUX
DAC
ADC CLOCK
DAC CLOCK
PLL
AD9861
CLKIN
Figure 1.
03606-0-001
of custom digital back ends or open market DSPs.
In half-duplex systems, the interface supports 20-bit parallel
transfers or 10-bit interleaved transfers. In full-duplex systems,
the interface supports an interleaved 10-bit ADC bus and an
interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin
count and, therefore, reduces the required package size on the
AD9861 and the device to which it connects.
The AD9861 can use either mode pins or a serial program-
mable interface (SPI) to configure the interface bus, operate the
ADC in a low power mode, configure the TxDAC interpolation
rate, and control ADC and TxDAC power-down. The SPI
provides more programmable options for both the TxDAC path
(for example, coarse and fine gain control and offset control for
channel matching) and the ADC path (for example, the internal
duty cycle stabilizer, and twos complement data format).
The AD9861 is packaged in a 64-lead LFCSP (low profile, fine
pitched, chip scale package). The 64-lead LFCSP footprint is
only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into
tightly spaced applications such as PCMCIA cards
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.






AD9861 Datasheet, Funktion
AD9861
TIMING SPECIFICATIONS
Table 5. AD9861-50 and AD9861-80
Parameter
INPUT CLOCK
CLKIN Clock Rate (PLL Bypassed)
PLL Input Frequency
PLL Ouput Frequency
TxPATH DATA
Setup Time (HD20 Mode, Time Required Before Data Latching
Edge)
Temp
Full
Full
Full
Full
Test Level
IV
IV
IV
V
Hold Time (HD20 Mode, Time Required After Data Latching Full V
Edge)
Latency 1× Interpolation (data in until peak output response)
Latency 2× Interpolation (data in until peak output response)
Latency 4× Interpolation (data in until peak output response)
RxPATH DATA
Output Delay (HD20 Mode, tOD)
Full
Full
Full
Full
V
V
V
V
Latency
Full V
Min Typ Max Unit
1 200 MHz
16 200 MHz
32 350 MHz
5 ns (see Clock
Distribution Block
section)
–1.5 ns (see Clock
Distribution Block
section)
7 DAC Clock Cycles
35 DAC Clock Cycles
83 DAC Clock Cycles
–1.5 ns (see Clock
Distribution Block
section)
5 ADC Clock Cycles
Table 6. Explanation of Test Levels
Level Description
I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 6 of 52

6 Page









AD9861 pdf, datenblatt
AD9861
70
60
50
40
IDEAL SNR
30
SNR
20
10
0
0 –5 –10 –15 –20 –25 –30 –35 –40 –45
INPUT AMPLITUDE (dBFS)
Figure 16. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
SNR Performance vs. Input Amplitude
62
AVE (–40°C)
61
AVE (+25°C)
60
59 AVE (+85°C)
58
57
56
2.7 3.0 3.3 3.6
ADC_AVDD VOLTAGE (V)
Figure 17. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
SNR Performance vs. ADC_AVDD and Temperature
–70.0
–70.5
–71.0
–71.5
AVE (+85°C)
–72.0
–72.5
AVE (+25°C)
–73.0
–73.5
–74.0
AVE (–40°C)
–74.5
–75.0
3.6 3.3 3.0 2.7
INPUT AMPLITUDE (dBFS)
Figure 18. AD9861-50 Rx Path Single-Tone THD Performance vs.
ADC_AVDD and Temperature
90
SFDR
80
–90
–80
70
THD
60
–70
–60
50 –50
40 –40
30 –30
20 –20
0 –5 –10 –15 –20 –25 –30 –35 –40
INPUT AMPLITUDE (dBFS)
Figure 19. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
THD and SFDR Performance vs. Input Amplitude
62 10.0
61
AVE (–40°C)
AVE (+25°C)
60
AVE (+85°C)
59
9.9
9.8
9.7
9.6
9.5
9.4
58
9.3
9.2
57
9.1
56 9.0
2.7 3.0 3.3 3.6
ADC_AVDD VOLTAGE (V)
Figure 20. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone
SINAD Performance vs. ADC_AVDD and Temperature
70
71
72
AVE (+85°C)
73
74
AVE (+25°C)
75
AVE (–40°C)
76
77
78
3.6 3.3 3.0 2.7
INPUT AMPLITUDE (dBFS)
Figure 21. AD9861-50 Rx Path Single-Tone SFDR Performance vs.
ADC_AVDD and Temperature
Rev. 0 | Page 12 of 52

12 Page





SeitenGesamt 30 Seiten
PDF Download[ AD9861 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD9860Mixed-Signal Front-End (MxFE) Processor for Broadband CommunicationsAnalog Devices
Analog Devices
AD9861Mixed-Signal Front-End (MxFE-TM) Baseband TransceiverAnalog Devices
Analog Devices
AD9862Mixed-Signal Front-End (MxFE) Processor for Broadband CommunicationsAnalog Devices
Analog Devices
AD9863Mixed-Signal Front-End (MxFE) Baseband TransceiverAnalog Devices
Analog Devices
AD9864IF Digitizing SubsystemAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche