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AD9236 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9236
Beschreibung A/D Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9236 Datasheet, Funktion
Data Sheet
12-Bit, 80 MSPS, 3 V A/D Converter
AD9236
FEATURES
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70.4 dBc to Nyquist
SFDR = 87.8 dBc to Nyquist
Low power: 366 mW
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
High end medical imaging equipment
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
DTV subsystems
GENERAL DESCRIPTION
The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS
analog-to-digital converter featuring a high performance sample-
and-hold amplifier (SHA) and voltage reference. The AD9236
uses a multistage differential pipelined architecture with output
error correction logic to provide 12-bit accuracy at 80 MSPS
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9236 is
suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9236
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
16
3
REF
SELECT
CORRECTION LOGIC
12
OUTPUT BUFFERS
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OTR
D11 (MSB)
D0 (LSB)
AGND
CLK
Figure 1.
PDWN MODE DGND
03066-0-001
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP
and is specified over the industrial temperature range
(−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9236 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.
4. The AD9236 is pin compatible with the AD9215, AD9235,
and AD9245. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
5. The DCS maintains overall ADC performance over a wide
range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9236 Datasheet, Funktion
AD9236
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1
CLK Pulse Width Low1
DATA OUTPUT PARAMETERS
Output Propagation Delay (tPD)2
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT OF RANGE RECOVERY TIME
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level Min
VI 80
V
V 12.5
V 4.0
V 4.0
V
V
V
V
V
V
AD9236BRU/AD9236BCP
Typ Max
1
3.5
7
1.0
0.3
7
2
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
ANALOG
INPUT
N N+1
N+2
N+8
N–1
tA
N+3
N+4 N+7
N+5 N+6
CLK
DATA
OUT
N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1
tPD = 6.0ns MAX
2.0ns MIN
Figure 2. Timing Diagram
N
03066-0-002
Table 5. Explanation of Test Levels
Test Level Definitions
I 100% production tested.
II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. C | Page 6 of 36

6 Page









AD9236 pdf, datenblatt
AD9236
0
AIN = –6.5dBFS
–10 SNR = 71.3dBFS
SFDR = 92.5dBc
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10
15 20 25
FREQUENCY (MHz)
30
35 40
03066-0-036
Figure 15. Two-Tone 8K FFT @ 30 MHz and 31 MHz
0
AIN = –6.5dBFS
–10 SNR = 71.0dBFS
SFDR = 79.3dBc
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
03066-0-037
Figure 16. Two-Tone 8K FFT @ 69 MHz and 70 MHz
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
Figure 17. Typical INL
3072
4096
03066-0-038
Data Sheet
SFDR (dBFS)
100
90
SFDR (dBc)
80
70
60
SFDR = 90dB
REFERENCE LINE
50
SNR (dBFS)
SNR (dBc)
40
–30 –27
–24 –21 –18 –15 –12
INPUT AMPLITUDE (dBFS)
–9 –6
03066-0-039
Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz
100
SFDR (dBFS)
90
SFDR (dBc)
80
70
SNR (dBFS)
60
SFDR = 90dB
REFERENCE LINE
50
SNR(dBc)
40
–30 –27 –24 –21 –18 –15 –12 –9
–6
INPUT AMPLITUDE (dBFS)
03066-0-040
Figure 19. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
Figure 20. Typical DNL
4096
03066-0-041
Rev. C | Page 12 of 36

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