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PDF A3250 Data sheet ( Hoja de datos )
| Número de pieza | A3250 | |
| Descripción | (A3250 / A3251) Chopper-Stabilized Unipolar Hall-Effect Switches | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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A3250 and A3251
Field-Programmable, Chopper-Stabilized
Unipolar Hall-Effect Switches
Features and Benefits
▪ Chopper stabilization for stable switchpoints throughout
operating temperature range
▪ Externally programmable operate point (through VCC
pin)
▪ On-board voltage regulator for 4.2 V to 24 V operation
▪ On-chip protection against:
▫ Supply transients
▫ Output short-circuits
▫ Reverse-battery condition
Description
The A3250 and A3251 are field-programmable, chopper-
stabilized, unipolar Hall-effect switches designed for use in
high-temperature applications. These devices use a chop-
per-stabilization technique to eliminate offset inherent in
single-element devices.
The A3250 and A3251 are externally programmable
devices. The devices have a wide range of programmabil-
ity of the magnetic operate point (BOP) while the hysteresis
remains fixed. This advanced feature allows for optimiza-
tion of the sensor switchpoint and can drastically reduce
the effects of variations found in a production environment,
such as magnet and device placement tolerances.
Package: 3 pin SOT89 (suffix LT) and
3 pin SIP (suffix UA)
These devices provide on-chip transient protection. A Zener
clamp on the power supply protects against overvoltage
conditions on the supply line. These devices also include
short-circuit protection on the output.
The output of the A3250 switches LOW when subjected
to a south-polarity magnetic field with a flux density that
exceeds the threshold for BOP, and switches HIGH when the
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Not to scale
VCC
Continued on the next page…
Functional Block Diagram
Program/Lock
Programming
Logic
Offset Adjust
Regulator
Amp
Low-Pass
Filter
Current Limit
VOUT
3250-DS Rev. 3
GND
1 page  
A3250 and
A3251
Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
Typical Characterization Data
All data are taken with A3250 devices, the average of 3 lots, 30 pieces per lot
35
30
25
20
15
10
5
0
-50
Average Bhys vs. Temperature
Program Code: 1, VCC = 12 V
-20 10 40 70 100 130 160
TA (°C)
35
30
25
20
15
10
5
0
-50
Average Bhys vs. Temperature
Program Code: 16, VCC = 12 V
-20 10 40 70 100 130 160
TA (°C)
35
30
25
20
15
10
5
0
-50
Average Bhys vs. Temperature
Program Code: 8, VCC = 12 V
-20 10
40 70
TA (°C)
100 130 160
Average BOP vs. Temperature
-40°C to 25°C and 150°C to 25°C
30
20
10
0
-10
-20
-30
-40°C to 25°C
Code 1
Code 8
Code 16
TA (°C)
150°C to 25°C
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5 Page 
A3250 and
A3251
Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
Enabling Addressing Mode. The first segment of code is a
keying sequence used to enable the bitfield addressing mode. As
shown in figure 4, this segment consists of one short VPH pulse,
seven or more VPM pulses, and one short VPH pulse, with no
supply interruptions. This sequence is designed to prevent the
device from being programmed accidentally, such as by noise on
the supply line.
V+
VPH
VPM
VPL
0
Minimum 7 pulses
t
Figure 4. Addressing mode enable pulse sequence
Address Selection. After addressing mode is enabled, the
target bitfield address, is indicated by a series of VPM pulses,
as shown in figure 3. When provisionally trying a value, this
sequence is followed by a short VPH pulse, which serves to
delimit the address and set the corresponding bitfield. When
permanently setting a bitfield, the VPH pulse is continued for a
longer period of time, suffienct to not only set the bitfield to 1,
but also to blow the bitfield fuse.
V+
VPH
VPM
VPL
0
Address 1
Address 2
Address n ( ≤ 63)
t
Figure 5. Pulse sequence to select addresses
Lock Bit Programming. After the desired BOP calibration value
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 65) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 6.
V+
VPH
Falling edge of final BOP address digit
VPM
VPL
7 pulses
65 pulses
0
Enable
Address
Blow
Encode Lock Bit
Figure 6. Pulse sequence to encode lock bit
t
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet A3250.PDF ] | |
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