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PDF AAT2511 Data sheet ( Hoja de datos )
| Número de pieza | AAT2511 | |
| Descripción | Step-Down DC/DC Converter | |
| Fabricantes | AAT | |
| Logotipo |  |
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AAT2511
Dual 600mA, 1MHz Step-Down DC/DC Converter
General Description
Features
SystemPower™
The AAT2511 is a member of AnalogicTech's Total
Power Management IC™ (TPMIC™) product fam-
ily. It is comprised of two 1MHz step-down con-
verters designed to minimize external component
size and cost. The input voltage ranges from 2.7V
to 5.5V. The output voltage ranges from 0.6V to the
maximum applied input voltage and is externally
adjustable.
Peak current mode control with internal compensa-
tion provides a stable converter with low ESR ceram-
ic output capacitors for extremely low output ripple.
Each channel has a low 25µA quiescent operating
current, which is critical for maintaining high effi-
ciency at light load.
For maximum battery life, each converter's high-
side P-channel MOSFET conducts continuously
when the input voltage approaches dropout (100%
duty cycle operation).
• Up to 97% Efficiency
• 25µA Quiescent Current Per Channel
• VIN Range: 2.7V to 5.5V
• VOUT Range: 0.6V to VIN
• Output Current: 600mA
• Low RDS(ON) 0.4Ω Integrated Power Switches
• Low Drop Out 100% Duty Cycle
• 1.0MHz Switching Frequency
• Shutdown Current <1µA
• Current Mode Operation
• Internal Reference Soft Start
• Short-Circuit Protection
• Fast Turn-On (100µs Typical)
• Over-Temperature Protection
• 3mm x 3mm, < 1mm high
• TDFN33-12 Package
• -40°C to +85°C Temperature Range
Both regulators have independent input and
enable inputs.
Applications
www.DataSheet4U.com
The AAT2511 is available in a Pb-free, thermally-
• Cellular Phones
enhanced 12-pin TDFN33 package, and is rated
• Digital Cameras
over the -40°C to +85°C temperature range.
• Handheld Instruments
• Microprocessor/DSP Core/IO Power
• PDAs and Handheld Computers
• Portable Media Players
Typical Application
VIN
C3
10µF
1.8V
C1
10µF
L1
4.7µH
R1
118k
R2
59.0k
U1
AAT2511
12
VIN1
9
VIN2
1
EN1
4
EN2
11
LX1
8
LX2
2
FB1
5
FB2
36
SGND1 SGND2
10
GND1
7
GND2
C8
0.1µF
2.5V
L2
10µH
R4
59.0k
R3
187k
C2
10µF
100
95
90
85 2.5V
80
75
70
65
60
0.1
AAT2511 Efficiency
(VIN = 3.3V)
1.8V
1 10 100
Load Current (mA)
1000
2511.2006.02.1.2
1
1 page  
AAT2511
Dual 600mA, 1MHz Step-Down DC/DC Converter
Typical Channel Characteristics
Efficiency vs. Load
(VOUT = 3.3V; L = 10µH)
100
90 VIN = 3.9V
80 VIN = 4.2V
70
60
0.1
1 10 100
Output Current (mA)
1000
DC Regulation
(VOUT = 3.3V; L = 10µH)
3.0
2.0
VIN = 4.2V
1.0
0.0
-1.0 VIN = 3.9V
-2.0
-3.0
0.1
1
10 100
Output Current (mA)
1000
Efficiency vs. Load
(VOUT = 2.5V; L = 10µH)
100
VIN = 3.3V
90
VIN = 3.0V VIN = 3.6V
80
70
60
0.1
1 10 100
Output Current (mA)
1000
DC Regulation
(VOUT = 2.5V; L = 10µH)
3.0
2.0 VIN = 3.3V
1.0 VIN = 3.6V
0.0
-1.0 VIN = 3.0V
-2.0
-3.0
0.1
1 10 100
Output Current (mA)
1000
Efficiency vs. Load
(VOUT = 1.5V; L = 4.7µH)
100
VIN = 2.7V
90
VIN = 3.6V
80
VIN = 4.2V
70
60
50
0.1
1 10 100
Output Current (mA)
1000
DC Regulation
(VOUT = 1.5V; L = 4.7µH)
3.0
2.0 VIN = 4.2V
1.0 VIN = 3.6V
0.0
-1.0 VIN = 2.7V
-2.0
-3.0
0.1
1
10 100
Output Current (mA)
1000
2511.2006.02.1.2
5
5 Page 
AAT2511
Dual 600mA, 1MHz Step-Down DC/DC Converter
The equation below solves for input capacitor size
for both channels. It makes the worst-case
assumptions that both converters are operating at
50% duty cycle and are synchronized.
1
CIN =
⎛ VPP
⎝ IO1 + IO2
- ESR⎞⎠ · 4 · FS
Because the AAT2511 channels will generally oper-
ate at different duty cycles and are not synchro-
nized, the actual ripple will vary and be less than
the ripple (VPP) used to solve for the input capaci-
tor in the equation above.
Always examine the ceramic capacitor DC voltage
coefficient characteristics when selecting the prop-
er value. For example, the capacitance of a 10µF
6.3V X5R ceramic capacitor with 5V DC applied is
actually about 6µF.
The maximum input capacitor RMS current is:
⎛⎝ ⎞⎠ ⎛⎝ ⎞⎠IRMS = IO1 ·
VO1
VIN
·
⎛⎝1 -
VO1 ⎞
VIN ⎠
+ IO2 ·
VO2
VIN
·
⎛⎝1 -
VO2 ⎞
VIN ⎠
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current of
both converters combined.
I =RMS(MAX)
I + IO1(MAX) O2(MAX)
2
This equation also makes the worst-case assump-
tion that both converters are operating at 50% duty
cycle and are synchronized. Since the converters
are not synchronized and are not both operating at
50% duty cycle, the actual RMS current will always
be less than this. Losses associated with the input
ceramic capacitor are typically minimal.
The term
VO
VIN
·
⎛⎝1 -
VO ⎞
VIN ⎠
appears in both the input
voltage ripple and input capacitor RMS current
equations. It is a maximum when VO is twice VIN.
This is why the input voltage ripple and the input
capacitor RMS current ripple are a maximum at
50% duty cycle.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT2511. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
the stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps
the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C3
and C8) can be seen in the evaluation board layout
in Figure 4. Since decoupling must be as close to
the input pins as possible, it is necessary to use
two decoupling capacitors. C3 provides the bulk
capacitance required for both converters, while C8
is a high frequency bypass capacitor for the second
channel (see C3 and C8 placement in Figure 4).
A laboratory test set-up typically consists of two
long wires running from the bench power supply to
the evaluation board input voltage pins. The induc-
tance of these wires, along with the low ESR
ceramic input capacitor, can create a high Q net-
work that may affect converter performance.
This problem often becomes apparent in the form
of excessive ringing in the output voltage during
load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short printed circuit board
trace feeding the input voltage is significantly lower
than the power leads from the bench power supply,
most applications do not exhibit this problem.
In applications where the input power source lead
inductance cannot be reduced to a level that does
not affect converter performance, a high ESR tan-
talum or aluminum electrolytic capacitor should be
placed in parallel with the low ESR, ESL bypass
ceramic capacitor. This dampens the high Q net-
work and stabilizes the system.
Output Capacitor
The output capacitor limits the output ripple and
provides holdup during large load transitions. A
4.7µF to 10µF X5R or X7R ceramic capacitor typi-
cally provides sufficient bulk capacitance to stabi-
2511.2006.02.1.2
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AAT2511.PDF ] | |
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