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PDF AD8324 Data sheet ( Hoja de datos )
| Número de pieza | AD8324 | |
| Descripción | Upstream Cable Line Driver | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Supports DOCSIS 2.0 and EuroDOCSIS specifications for
reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output
−59 dBc SFDR at 21 MHz
−54 dBc SFDR at 65 MHz
Output noise level at minimum gain 1.3 nV/√Hz
Maintains 75 Ω output impedance in transmit-enable and
transmit-disable condition
Upper bandwidth of 100 MHz (full gain range)
3.3 V supply operation
Supports SPI® interfaces
APPLICATIONS
DOCSIS 2.0 and EuroDOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GENERAL DESCRIPTION
The AD8324 is a low cost amplifier designed for coaxial line
driving. The features and specifications make the AD8324
ideally suited for DOCSIS® 2.0 and EuroDOCSIS applications.
The gain of the AD8324 is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The AD8324 accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 1:1
transformer.
Distortion performance of –54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quiescent
current to 30 μA and a full power-down function that reduces
power-down current to 2.5 mA.
The AD8324 is packaged in a low cost, 20-lead LFCSP and a
20-lead QSOP. The AD8324 operates from a single 3.3 V supply.
3.3 V, Upstream,
Cable Line Driver
AD8324
FUNCTIONAL BLOCK DIAGRAM
BYP
VIN+
VIN–
DIFF
OR SINGLE
INPUT
AMP
VERNIER
ZIN (SINGLE) = 550Ω
ZIN (DIFF) = 1100Ω
AD8324
VOUT+
ATTENUATION
CORE
OUTPUT
STAGE
VOUT–
8
ZOUT DIFF =
75Ω
DECODE
8
DATA LATCH
POWER-
DOWN LOGIC
RAMP
8
SHIFT
REGISTER
GND DATEN SDATA CLK
Figure 1.
TXEN SLEEP
–40
–50 VOUT = 61dBmV @ DEC 60
THIRD HARMONIC
–60
–70
VOUT = 61dBmV @ DEC 60
SECOND HARMONIC
–80
5 15 25 35 45 55
FREQUENCY (MHz)
Figure 2. Worst Harmonic Distortion vs. Frequency
65
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD8324
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
OPERATING TEMPERATURE RANGE
Test Conditions/Comments
Maximum gain
Minimum gain
Transmit disable (TXEN = 0)
SLEEP mode (power down)
20-lead LFCSP
20-lead QSOP
1 TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB at 10 MHz.
2 Guaranteed by design and characterization to ±6 sigma for TA = 25°C.
3 Guaranteed by design and characterization to ±3 sigma for TA = 25°C.
4 Measured through a 1:1 transformer.
5 Specification is worst case over all gain codes.
6 VIN = 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 3.3 V, unless otherwise noted.
Table 2.
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (VINH = 3.3 V), CLK, SDATA, DATEN
Logic 0 Current (VINL = 0 V), CLK, SDATA, DATEN
Logic 1 Current (VINH = 3.3 V), TXEN
Logic 0 Current (VINL = 0 V), TXEN
Logic 1 Current (VINH = 3.3 V), SLEEP
Logic 0 Current (VINL = 0 V), SLEEP
Min Typ
3.13 3.3
195 207
25 39
1 2.5
30
−40
−25
Data Sheet
Max Unit
3.47 V
235 mA
50 mA
4 mA
500 µA
+85 °C
+70 °C
Min
2.1
0
0
−600
50
−250
50
−250
Typ Max
3.3
0.8
20
−100
190
−30
190
−30
Unit
V
V
nA
nA
µA
µA
µA
µA
Rev. C | Page 4 of 16
5 Page 
AD8324
180
f = 10MHz
160 TXEN = 1
140
120
100
80
60
40
20
0
0 6 12 18 24 30 36 42 48 54 60
GAIN CONTROL (Decimal Code)
Figure 19. Output Referred Voltage Noise vs. Gain Control
210
190 TA = 25°C
170
150
130
110
90
70
50
30
0 6 12 18 24 30 36 42 48 54
GAIN CONTROL (Decimal Code)
Figure 20. Quiescent Supply Current vs. Gain Control
60
Data Sheet
110
100
90
80
70
60
50
DOCSIS 2.0 BETWEEN BURST
40 TRANSIENT SPECIFICATION
30
20 AD8324
10
0
0 6 12 18 24 30 36 42 48 54
GAIN CONTROL (Decimal Code)
Figure 21. Between Burst Transient vs. Gain Control
60
Rev. C | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD8324.PDF ] | |
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