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PDF ADCMP580 Data sheet ( Hoja de datos )
| Número de pieza | ADCMP580 | |
| Descripción | (ADCMP580 - ADCMP582) Ultrafast SiGe Voltage Comparators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Ultrafast SiGe
Voltage Comparators
ADCMP580/ADCMP581/ADCMP582
FEATURES
180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
200 fs random jitter (RJ)
−2 V to +3 V input range with +5 V/−5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
FUNCTIONAL BLOCK DIAGRAM
VTP TERMINATION
VP NONINVERTING
INPUT
VN INVERTING
INPUT
ADCMP580/
ADCMP581/
ADCMP582
CML/ECL/
PECL
VTN TERMINATION
HYS
LE INPUT
LE INPUT
Figure 1.
Q OUTPUT
Q OUTPUT
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GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on Analog Devices’ proprietary XFCB3
Silicon Germanium (SiGe) bipolar process. The ADCMP580
features CML output drivers; the ADCMP581 features reduced
swing ECL (negative ECL) output drivers; and the ADCMP582
features reduced swing PECL (positive ECL) output drivers.
All three comparators offer 180 ps propagation delay and
100 ps minimum pulse width for 10 Gbps operation with
200 fs random jitter (RJ). Overdrive and slew rate dispersion
are typically less than 15 ps.
The ±5 V power supplies enable a wide −2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.
The CML output stage is designed to directly drive 400 mV
into 50 Ω transmission lines terminated to ground. The NECL
output stages are designed to directly drive 400 mV into 50 Ω
terminated to −2 V. The PECL output stages are designed to
directly drive 400 mV into 50 Ω terminated to VCCO − 2 V.
High speed latch and programmable hysteresis are also
provided. The differential latch input controls are also 50 Ω
terminated to an independent VTT pin to interface to either
CML or ECL or to PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in
a 16-lead LFCSP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
ADCMP580/ADCMP581/ADCMP582
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in the figure.
LATCH ENABLE
LATCH ENABLE
tS
tH
tPL
50%
DIFFERENTIAL
INPUT VOLTAGE
VN
VOD
VN ± VOS
Q OUTPUT
Q OUTPUT
tPDL
tPLOH
tPDH
tF
tPLOL
tR
Figure 2. Comparator Timing Diagram
50%
50%
Table 2. Timing Descriptions
Symbol Timing
tPDH Input to Output High Delay
tPDL Input to Output Low Delay
tPLOH Latch Enable to Output High Delay
tPLOL Latch Enable to Output Low Delay
tH Minimum Hold Time
tPL Minimum Latch Enable Pulse Width
tS Minimum Setup Time
tR Output Rise Time
tF Output Fall Time
VN Normal Input Voltage
VOD Voltage Overdrive
Description
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal
low-to-high transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal
low-to-high transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the
input signal must remain unchanged to be acquired and held at the outputs.
Minimum time that the latch enable signal must be high to acquire an input
signal change.
Minimum time before the negative transition of the latch enable signal that an
input signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured
at the 20% and 80% points.
Amount of time required to transition from a high to a low output as measured
at the 20% and 80% points.
Difference between the input voltages VP and VN for output true.
Difference between the input voltages VP and VN for output false.
Rev. 0 | Page 5 of 16
5 Page 
ADCMP580/ADCMP581/ADCMP582
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP58x family of comparators is designed for very
high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes,
particularly for the negative supply (VEE), the output supply
plane (VCCO), and the ground plane (GND). Individual supply
planes are recommended as part of a multilayer board. Provid-
ing the lowest inductance return path for the switching currents
ensures the best possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. A 1 μF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 μF bypass capacitors should
be placed as close as possible to each of the VEE, VCCI, and VCCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
ADCMP58x FAMILY OF OUTPUT STAGES
Specified propagation delay dispersion performance is achieved
by using proper transmission line terminations. The outputs of
the ADCMP580 family comparators are designed to directly
drive 400 mV into 50 Ω cable or microstrip/stripline transmis-
sion lines terminated with 50 Ω referenced to the proper return.
The CML output stage is shown in the simplified schematic
diagram in Figure 24. Each output is back-terminated with
50 Ω for best transmission line matching. The outputs of the
ADCMP581/ADCMP582 are illustrated in Figure 25; they
should be terminated to −2 V for ECL outputs of ADCMP581
and VCCO − 2 V for PECL outputs of ADCMP582. As an alter-
native, Thevenin equivalent termination networks may also be
used. If these high speed signals must be routed more than a
centimeter, then either microstrip or stripline techniques are
required to ensure proper transition times and to prevent
excessive output ringing and pulse width-dependent
propagation delay dispersion.
GND
50Ω 50Ω
Q
Q
16mA
VEE
Figure 24. Simplified Schematic Diagram
of the ADCMP580 CML Output Stage
GND / Vcco
Q
Q
VEE
Figure 25. Simplified Schematic Diagram of the
ADCMP581/ADCMP582 ECL/PECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode and are
internally terminated with 50 Ω resistors to the VTT pin. When
using the ADCMP580, VTT should be connected to ground.
When using the ADCMP581, VTT should be connected to
−2 V. When using the ADCMP582, VTT should be connected
externally to VCCO − 2 V, preferably with its own low inductance
plane.
When using the ADCMP580/ADCMP582, the latch function
can be disabled by connecting the LE pin to VEE with an
external pull-down resistor and leaving the LE pin discon-
nected. To prevent excessive power dissipation, the resistor
should be 1.5 kΩ for the ADCMP580 and 1 kΩ for the
ADCMP582. When using the ADCMP581 comparators, the
latch can be disabled by connecting the LE pin to GND with
an external 450 Ω resistor and leaving the LE pin disconnected.
The idea is to create an approximate 0.5 V offset using the
internal resistor as half of the voltage divider. The VTT pin
should be connected as recommended.
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ADCMP580.PDF ] | |
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