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83C154 Schematic ( PDF Datasheet ) - TEMIC Semiconductors

Teilenummer 83C154
Beschreibung CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
Hersteller TEMIC Semiconductors
Logo TEMIC Semiconductors Logo 




Gesamt 24 Seiten
83C154 Datasheet, Funktion
80C154/83C154
CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller
Description
TEMIC’s 80C154 and 83C154 are high performance
CMOS single chip µC. The 83C154 retains all the
features of the 80C52 with extended ROM capacity (16
K bytes), 256 bytes of RAM, 32 I/O lines, a 6-source
2-level interrupts, a full duplex serial port, an on-chip
oscillator and clock circuits, three 16 bit timers with extra
features : 32 bit timer and watchdog functions. Timer 0
and 1 can be configured by program to implement a 32 bit
timer. The watchdog function can be activated either with
timer 0 or timer 1 or both together (32 bit timer).
In addition, the 83C154 has 2 software-selectable modes
of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM is saved, and the timers, the serial port and the
interrupt system continue to function. In the power down
mode the RAM is saved and the timers, serial port and
interrupt continue to function when driven by external
clocks. In addition as for the TEMIC 80C51/80C52, the
stop clock mode is also available.
The 80C154 is identical to the 83C154 except that it has
no on-chip ROM. TEMIC’s 80C154 and 83C154 are
manufactured using SCMOS process which allows them
to run from 0 up to 36 MHz with Vcc = 5 V.
D 80C154 : ROMless version of the 83C154µ
D 80C154/83C154-12 : 0 to 12 MHz
D 80C154/83C154-16 : 0 to 16 MHz
D 80C154/83C154-20 : 0 to 20 MHz
D 80C154/83C154-25 : 0 to 25 MHz
D 80C154/83C154-30 : 0 to 30 MHz
D 80C154/83C154-36 : 0 to 36 MHz
D 80C154/83C154-L16 : Low power version
VCC : 2.7-5.5 V Freq : 0-16 MHz
For other speed and temperature range availability please consult your
sales office.
Features
www.DataSheet4U.com
D Power control modes
D 256 bytes of RAM
D 16 Kbytes of ROM (83C154)
D 32 Programmable I/O lines (programmable impedance)
D Three 16 bit timer/counters (including watchdog and 32 bit
timer)
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range : commercial, industrial, automotive,
military
Optional
D Secret ROM : Encryption
D Secret TAG : Identification number
MATRA MHS
Rev.F (14 Jan. 97)
1






83C154 Datasheet, Funktion
80C154/83C154
PCON : Power Control Register
(MSB)
(LSB)
The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
SMOD HPD RPD – GF1 GF0 PD IDL
instruction that writes to PCON.0 can also set or clear one
or both flag bits. When Idle mode is terminated by an
Symbol
Position
Name and Function
enabled interrupt, the service routine can examine the
status of the flag bits.
SMOD
HPD
RPD
GF1
GF0
PD
IDL
PCON.7
PCON.6
PCON.5
PCON.3
PCON.2
PCON.1
PCON.0
Double Baud rate bit. When set to
a 1, the baud rate is doubled when
the serial port is being used in
either modes 1, 2 or 3.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
Hard power Down bit. Setting this cycles (24 oscillator periods) to complete the reset
bit allows CPU to enter in Power
Down state on an external event
(1 to 0 transition) on bit T1
operation.
The third way to terminate the Idle mode is the activation
(p. 3.5) the CPU quit the Hard
of any disabled interrupt when recover is programmed
Power Down mode when bit T1
p. 3.5) goes high or when reset is
activated.
Recover from Idle or Power Down
(RPD = 1). This will cause PCON.0 to be cleared. No
interrupt is serviced. The next instruction is executed. If
interrupt are disabled and RPD = 0, only a reset can
bit. When 0 RPD has no effetc.
cancel the Idle mode.
When 1, RPD permits to exit from
idle or Power Down with any non
enabled interrupt source (except
Power Down Mode
time 2). In this case the program
start at the next address. When
The instruction that sets PCON.1 is the last executed prior
interrupt is enabled, the
to entering power down. Once in power down, the
appropriate interrupt routine is
oscillator is stopped. The contents of the onchip RAM and
serviced.
the Special Function Register is saved during power down
General-purpose flag bit.
General-purpose flag bit.
mode. The three ways to terminate the Power Down mode
Power Down bit. Setting this bit
are the same than the Idle mode. But since the onchip
activates power down operation. www.DaotasScheieltl4aU.tcoomr is stopped, the external interrupts, timers and
Idle mode bit. Setting this bit
serial port must be sourced by external clocks only, via
activates idle mode operation.
INT0, INT1, T0, T1.
If 1’s are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(000X0000).
In the Power Down mode, VCC may be lowered to
minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power down
Idle Mode
mode is entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator. Reset
The instruction that sets PCON.0 is the last instruction should not be released until the oscillator has restarted
executed before the Idle mode is activated. Once in the and stabilized.
Idle mode the CPU status is preserved in its entirety : the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. In the idle mode, the internal clock signal
is gated off to the CPU, but interrupt, timer and serial port
functions are maintained. Table 1 describes the status of
the external pins during Idle mode. There are three ways
to terminate the Idle mode. Activation of any enabled
interrupt will cause PCON.0 to be cleared by hardware,
terminating Idle mode. The interrupt is serviced, and
following RETI, the next instruction to be executed will
When using voltage reduction : interrupt, timers and
serial port functions are guaranteed in the VCC
specification limits.
Table 1 describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the port switches from
0 to 1, the port pin is held high during the power down
mode by the strong pullup, T1, shown in figure 4.
be the one following the instruction that wrote 1 to
PCON.0.
6 MATRA MHS
Rev.F (14 Jan. 97)

6 Page









83C154 pdf, datenblatt
80C154/83C154
D If C/T = 0, the WATCHDOG is a TIMER that is
incremented every machine cycle. If C/T = 1, the
WATCHDOG is a counter that is incremented by an
external signal of which the frequency cannot exceed
OSC ÷ 24.
D The overflow of the TIMER/COUNTER is signalled
by raising flag TF1 to 1. The reset of the 83C154 is
executed during the next machine cycle and lasts for
the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal
RAM is not affected and the special register assume
the values shown in Table 3.
D As there are no precautions for protecting bit WDT
from spurious writing in the IOCON register, special
care must be taken when writing the program. In
particular, the user should use the IOCON register bit
handling instructions :
– SETB and CLR x
in preference to the byte handling instructions :
– MOV IOCON, # XXH, ORL IOCON, #XXH,
– ANL IOCON, #XXH
External Counting in Power-down Mode
(PD = PCON.1 = 1)
Table 3. Content of the SFRS after a reset triggered D In the power-down mode, the oscillator is turned off
by the watchdog.
and the 83C154’s activity is frozen. However, if an
REGISTER
CONTENT
external clock is connected to one of the two inputs,
T1/T0, TIMER/COUNTERS 0 and 1 can continue to
PC 000H operate.
ACC
B
PSW
SP
DPTR
00H
00H
00H
07H
0000H
In this case, counting becomes asychronous and the
maximum, admissible frequency of the signal is
OSC : 24.
D The overflow of either counter TF0 or TF1 causes an
P0-P3
IP
IE
0FFH
0X000000B
0X000000B
interrupt to be serviced or forces a reset if the counter
is in the WATCHDOG MODE (T32 = ICON.7 = 1).
TMOD
00H
TCON
00H
T2CON
00H
TH0
00H www.DataSheet4U.com
TL0 00H
TH1 00H
TL1 00H
TH2 00H
TL2 00H
RCAP2H
00H
RCAP2L
00H
SCON
00H
SBUF
Indeterminate
IOCON
00H
PCON
000X0000B
12 MATRA MHS
Rev.F (14 Jan. 97)

12 Page





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