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DS26519 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS26519
Beschreibung single-chip 16-port framer and line interface unit (LIU) combination
Hersteller Maxim Integrated Products
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Gesamt 70 Seiten
DS26519 Datasheet, Funktion
DS26519
16-Port T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS26519 is a single-chip 16-port framer and line
interface unit (LIU) combination for T1, E1, and J1
16 Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
applications. Each port is independently configurable,
Independent T1, E1, or J1 Selections for Each
supporting both long-haul and short-haul lines. The
Transceiver
DS26519 is nearly software compatible with the
DS26528 and its derivatives.
Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
APPLICATIONS
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
Routers
and 75Ω E1 Coaxial Applications
Channel Service Units (CSUs)
Hitless Protection Switching
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
T1/E1/J1
NETWORK
DS26519
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode
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Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
T1/J1/E1
Transceiver x16 BACKPLANE
TDM
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
ORDERING INFORMATION
PART
DS26519G
DS26519G+
DS26519GN
DS26519GN+
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
484 HSBGA
484 HSBGA
484 HSBGA
484 HSBGA
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
+ Denotes lead-free/RoHS compliant device.
Features Continued in Section 2.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS26519 Datasheet, Funktion
DS26519 16-Port T1/E1/J1 Transceiver
Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 278
Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 278
Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 279
Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 279
Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode ............................................................... 280
Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode ............................................................ 281
Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 ........................................................ 281
Figure 11-24. E1 Transmit-Side Timing................................................................................................................... 282
Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 282
Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 283
Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 283
Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode .............................................................. 284
Figure 11-29. E1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 285
Figure 11-30. E1 G.802 Timing ............................................................................................................................... 286
Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ........................................................ 286
Figure 13-1. SPI Interface Timing Diagram ............................................................................................................. 290
Figure 13-2. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 292
Figure 13-3. Intel Bus Write Timing (BTS = 0)......................................................................................................... 292
Figure 13-4. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 293
Figure 13-5 Motorola Bus Write Timing (BTS = 1) .................................................................................................. 293
Figure 13-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 295
Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 Mode) ................................................................... 296
Figure 13-8. Receive Framer Timing—Line Side .................................................................................................... 296
Figure 13-9. Transmit Formatter Timing—Backplane ............................................................................................. 298
Figure 13-10. Transmit Formatter Timing—Elastic Store Enabled.......................................................................... 298
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Figure 13-11. BPCLKn Timing................................................................................................................................. 299
Figure 13-12. Transmit Formatt Timing—Line Side ................................................................................................ 299
Figure 13-13. JTAG Interface Timing Diagram........................................................................................................ 300
Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 302
Figure 14-2. TAP Controller State Diagram............................................................................................................. 305
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DS26519 pdf, datenblatt
DS26519 16-Port T1/E1/J1 Transceiver
Signaling freezing
Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
User-selectable synthesized clock output
2.7 HDCL Controllers
One HDLC controller engine for each T1/E1 port
Independent 64-byte Rx and Tx buffers with interrupt support
Access FDL, Sa, or single DS0 channel
Compatible with polled or interrupt driven environments
2.8 Test and Diagnostics
IEEE 1149.1 support
Per-channel programmable on-chip bit error-rate testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion single and continuous
Total-bit and errored-bit counts
Payload error insertion
Error insertion in the payload portion of the T1 frame in the transmit path
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel loopback)
2.9 Microcontroller Parallel Port
8-bit parallel control port
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Intel or Motorola nonmultiplexed support
Flexible status registers support polled, interrupt, or hybrid program environments
Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
2.10
Slave Serial Peripheral Interface (SPI) Features
Software access to device ID and silicon revision
Three-wire synchronous serial data link operating in full-duplex slave mode up to 5Mbps
Glueless connection and fully compliant to Motorola popular communication processors such as MPC8260
and microcontrollers such as M68HC11
Software provision ability for active phase of the serial clock (i.e., rising edge vs. falling edge), bit ordering
of the serial data (most significant first vs. least significant bit first)
Flexible status registers support polled, interrupt, or hybrid program environments
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